MAX5167
hold capacitor to acquire the input signal. To guarantee
an accurate sample, maintain sample mode for at least
4µs. The output of the sample/hold amplifier tracks the
input after 4µs. Only the addressed channel on the
selected multiplexer samples the input; all other channels
remain in hold mode.
Hold Mode
No matter what the condition of the other control lines,
S/H = high places the MAX5167 into an all-channel
hold mode. Hold mode disables the multiplexer and
disconnects all 32 sample/holds from the input. When a
channel is disconnected, the hold capacitor maintains
the sampled voltage at the output with a 1mV/s typical
droop rate (towards V
DD
).
Hold Step
When switching between sample mode and hold mode,
the voltage of the hold capacitor changes due to
charge injection from stray capacitance. This voltage
change, called hold step, is minimized by limiting the
amount of stray capacitance seen by the hold capacitor.
The MAX5167 limits the hold step to 0.25mV (typ). An
output capacitor to ground can be used to filter out this
small hold-step error.
Output
The MAX5167 contains an output buffer for each multi-
plexer channel (32 total), so the hold capacitor sees a
high-impedance input that reduces the droop rate. The
capacitor droops at 1mV/s (typ) while in hold mode. The
buffer also provides a low output impedance; however,
the device contains output resistors in series with the
buffer output (Figure 1) for selected output filtering. To
provide greater design flexibility, the MAX5167 is avail-
able with an output impedance of 50Ω, 500Ω, or 1kΩ.
Output loads increase the analog supply current (I
DD
and I
SS
). Excessive loading of the output(s) drastically
increases power dissipation. Do not exceed the maximum
power dissipation specified in the Absolute Maximum
Ratings.
The resistor-divider formed by the output resistor (R
O
)
and load impedance (R
L
) scales the sampled voltage
(V
SAMP
). Determine the output voltage (V
OUT_
) as follows:
Voltage Gain = A
V
= R
L
/ (R
L
+ R
O
)
V
OUT_
= V
SAMP
✕
A
V
The maximum output voltage range depends on the ana-
log supply voltages available and the scaling factor used:
(V
SS
+ 0.75V)
✕
A
V
≤ V
OUT_
≤ (V
DD
- 2.4V)
✕
A
V
when RL = ∞, then A
V
= 1, and this equation becomes:
(V
SS
+ 0.75V) ≤ V
OUT
≤ (V
DD
- 2.4V)
Output Clamp
The MAX5167 clamps the output between two externally
applied reference voltages. Internal diodes connect all
outputs to the clamping voltages, restricting the output
voltage to:
(V
CH
+ 0.7V) ≤ V
OUT_
≤ (V
CL
- 0.7V)
When the clamping voltage exceeds the maximum output
voltage, the maximum output voltage will be the limiting
factor. To disable output clamping, connect CH to V
DD
and CL to V
SS
to set the clamping voltages beyond the
maximum output voltage range. The clamping diodes
allow the MAX5167 to be used with other devices
requiring restricted input voltages.
Timing Definitions
Acquisition time (t
AQ
) is the time the MAX5167 must
remain in sample mode for the hold capacitor to
acquire an accurate sample. The hold-mode settling
time (t
H
) is the time necessary for the output voltage to
settle to its final value. Aperture delay (t
AP
) is the time
interval required to disconnect the input from the hold
capacitor. The hold pulse width (t
PW
) is the time the
MAX5167 must remain in hold mode while the address
is changed. Data setup time (t
DS
) is the time an
address must be maintained at the digital input pins
before the address becomes valid. Data hold time (t
DH
)
is the time an address must be maintained after the
device is placed in hold mode (Figure 2).
Applications Information
Multiplexing a DAC
Figure 3 shows a typical demultiplexer application.
Different digital codes are converted by the digital-to-
analog converter (DAC) and then stored on 32 different
channels of the MAX5167. The 40mV/s (max) droop
rate requires refreshing the hold capacitors every
250ms before the voltage droops by 1/2LSB for an 8-bit
DAC with a 5V full-scale voltage.
Virtual 64 Output Sample and Hold
Two MAX5167s can be configured to operate as a single
64 output sample and hold. The upper and lower
addressed devices are identified by CONFIG’s logic
level. Connect the CONFIG pin of the upper device low,
making its SELECT pin active-high. Connect the CONFIG
pin of the lower device high to make the SELECT pin
active-low. Figure 4 shows how to configure the devices.
The devices now use only six address lines and a single
S/H control to decode 64 outputs. Address lines A0–A4
from the control logic connect to ADDR0–ADDR4 on
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
8 _______________________________________________________________________________________
