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NCP1282BDR2G

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NCP1282
http://onsemi.com
16
V
CS K IP(val ley)
once the CS K I P voltage reaches the turn on
thres h old of the latch. The external latch is cleared by
bringing the UVOV voltage below V
UV
and disablin g V
REF
.
V
REF
C
REF
CSKIP
C
CSKIP
OUTY
V
CC
INA
OE
MC74VHC1GT126
Figure 38. External Latch Implemented using
ON Semiconductor’s MiniGatet Buffer
The latch in Figure 38 consists of a TTL le vel tri--state
output buffer from ON Semiconductor’s MiniGatet
family. The enable (OE) and output (OUTY) terminals are
connected to CSKIP and the V
CC
and INA pins are
connected to V
REF
. The output of the buffer is in a high
impedance m ode when OE is low. Once a continuous
current limit condition is detected, the CSKIP timer is
enabl ed and CSKIP begins charging. Once the voltage on
CSKIP reaches the enable threshold of the buffer, the
output of the buffer is pulled to V
REF
, latching the CSKIP
timer. The OE threshold of the buffer is typically 1.5 V.
V
REF
C
REF
C
CSKIP
CSKIP
BSS84L
M2
24.9 kΩ
2N7002L
R
pull--up
M1
Figure 39. External Latch Implemented using
Discrete N and P--Channel MOSFETs
A latch implemented using discrete N and P--channel
MOSFETs is shown in Figure 39. The latch is enabled once
the CSKIP voltage reaches the threshold of M1. Once M1
turns on, it pulls low the gate of M2. CSKIP is then pulled
to V
REF
by M2. It is important to size R
pull--up
correctly. If
R
pull--up
is too big, it will not keep M2 off while V
REF
charges. This will cause the controller to latch during initial
power--up. In this particular implementation the turn on
threshold of M1 is 2 V and R
pull--up
is sized to 24.9 k.
Leading Edge Blanking
The current sense signal is prone to lea ding edge spike s
caused by the power switch transitions. The current signal
is usually filtered using an RC low–pass filter to avoid
premature triggering of the current limit circuit. However,
the low pass filter will inevitably change the shape of the
current pulse and also a dd cost and compl exity. T he
NCP1282 uses LEB circuitry that blocks out the first 70 ns
(typ) of each current pulse. This removes the leading edge
spikes without altering the current waveform. The blanking
period is disabled during soft--start as the blanking period
may be longer than t he startup duty cycle. It is al so disabled
if the out put of the Saturation Comparator is l ow, indicating
that the output is not yet in regulation. This occurs during
power up or during an out put overload c ondition.
Supply Voltage and Startup Circuit
The NCP1282 internal startup regulator eliminates the
need for external startup components. In addition, this
regula tor increases the efficiency of the supply as it uses no
power when in the normal mode of operation, but instead
uses power supplied by an auxiliary winding. The
NCP1282 incorporates an optimized startup circuit that
reduce s the requirement of the supply capacitor,
particularly important in size constrained a pplications.
The minimum supply voltage of the NCP1282 is
optimized for driving high voltage MOSFETs. It is not
uncommon for high voltage MOSFETs to have a gate
plateau voltage of 6 V. In addition, high voltage
applications may require a high side drive circuit with a
voltage drop of up to two diodes. If the minimum supply
voltage is too low, there may not be enough voltage for
driving the external MOSFETs causing the system to
malfunction. The NCP1282 elimin ates this problem with a
minimum supply voltage of 8.5 V.
The startup regulator consists of a constant current
source that supplies current from the input line voltage
(V
in
) to the supply capacitor on the V
AUX
pin (C
AUX
). The
startup current (I
start
) is typically 10 mA.
Once C
AUX
is charged to 11.0 V (V
AUX(on)
), the startup
regulator is disabled and the outputs are enabled if there are
no UV, OV, CSKIP or thermal shutdown faults. The startup
regulator remains disabled until the lower voltage
threshold (V
AUX(off1)
) of 9.5 V is reached. Once reached,
the startup circ uit is enabled and a soft--stop e vent is
initiated. If the bias current requirement out of C
AUX
is
greater than the startup current, V
AUX
will discharge until
reaching the lower voltage threshold (V
AUX(off2)
)of8.5V.
Upon reaching V
AUX(off2)
, the outputs are disabled. Once
the outputs are disabled, the bias current of the IC is
reduce d, allowing V
AUX
to charge back up. This mode of
operation allows a dramatic reduction in the size of C
AUX
as not all the power required for startup needs to be stored
by C
AUX
. This mode of operation is known as Dynamic
Self Supply (DSS). Figure 40 shows the rela tionship
between V
AUX(on)
,V
AUX(off1)
,V
AUX(off2)
and UV. As
shown in Figure 40, the outputs are not enabled until the
UV fault is removed and V
AUX
reaches V
AUX(on)
.
NCP1282
http://onsemi.com
17
Figure 40. Startup Circuit Waveforms
V
AUX(off1)
V
AUX(on)
V
AUX
V
inhibit
V
UVOV
V
REF
V
SS
V
out1
The startup regulator is disabled by bi asing V
AUX
above
V
AUX(on)
. This feature allows the NCP1282 to operate from
an independe nt 12 V supply. If operating from an
indepe ndent supply, the V
in
and V
AUX
pins should be
connec ted together. The independent supply should
maintain V
AUX
above V
AUX(on)
. Otherwise, the Output
Latch will not be SET and the outputs will remain OFF after
a fault condition is removed.
The startup circuit sources current into the V
AUX
pin. It
is recommended to place a diode between C
AUX
and the
auxiliary supply as shown in Figure 41. This allows the
NCP1282 to cha rge C
AUX
while preventing the startup
regulator from sourcing current into the auxiliary supply.
Disable
V
in
I
start
V
AUX
I
AUX
C
AUX
I
supply
Auxiliary Supply or
Independent Supply
Figure 41. Recommended V
AUX
Configuration
C
AUX
provides power to the controller while operating
in the self--bias or DSS m ode. During the converter
powerup, C
AUX
must be sized such that a V
AUX
voltage
greater than V
AUX(off2)
is maintained while the auxiliary
supply voltage is building up. Otherwise, V
AUX
will
collapse and the controller will turn OFF. Also, the V
AUX
discharge time (from 11.0 V to 9.5 V) must be greater that
the soft--start charge period to assure the converter turns
ON. The IC bias current, gate charge load on the outputs,
and the 5.0 V reference load must be considered to
correctly size C
AUX
. The current consumption due to
external gate charge is calculated using Equation 1.
I
AUX(gate charge)
= f ⋅ Q
G
(eq. 1)
wh ere, f is the operating frequency and Q
G
is the gate charg e.
An internal supervisory circuit monitors V
AUX
and
prevent s excessive power dissipation if the V
AUX
pin is
accidentally shorted. While V
AUX
is below 1.2 V, the
startup circuit is disabled and a current source (I
inhibit
)
charges V
AUX
with a minimum current of 50 mA. Once
V
AUX
reaches 1.2 V the startup circuit is enabled.
Therefore it is imperative that V
AUX
is not loaded (driver,
resistor divider, etc.) with more than 50 mA while V
AUX
is
below 1.2 V. Otherwise, V
AUX
will not charge. If a load
greater than 50 mA is present, a resistor can be placed
between the V
in
and V
AUX
pins t o help charge V
AUX
to
1.2 V.
The startup circuit is rated at a maximum voltage of
500 V. If the device operates in the DSS mode, powe r
dissipation should be controlled to avoid e xceeding the
maximum power dissipat ion of the cont roller. If dissipat ion
on the controller is excessive, a resistor can be placed in
series with the V
in
pin. This will reduce power dissipation
on the controller and transfer it to the series resistor.
Line Under/Overvoltage Detector
The same pin is used for bot h line undervoltage (UV) and
overvoltage (OV) dete ction using a novel architecture
(patent pending). This architecture allows both the UV and
OV levels to be set independently. Both the UV and OV
detectors have a 100 mV hysteresis.
NCP1282
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18
The line voltage is sampled using a resistor divider as
shown in Figure 42.
--
+
OV Comparator
V
OVCOMP
3.0 V
+
--
--
+
UV Comparator
V
UVCOMP
2.0 V
+
--
--
+
2.5 V
+
--
UVOV
C
UVOV
R1
R2
V
in
I
offset(UVOV)
Figure 42. Line UVOV Detectors
A UV condition exists if the UVOV voltage is below
V
UV
, typically 2.0 V. The ratio of R1 and R2 determines the
UV turn threshold. Once the UVOV voltage exceeds 2.5 V,
an internal current source (I
offset(UVOV)
) sinks 50 mA into
the UVOV pin. This will clamp the UVOV voltage at 2.5 V
while the current across R1 is less than I
offset(UVOV)
.Ifthe
input voltage continues to increase, the 50 mA source will
be overridden and the voltage at the UVOV pin will
increase. An OV condition exists if the UVOV voltage
exceeds V
OV
, typically 3.0 V. Figure 43 shows the
relationship between UVOV and V
in
.
Figure 43. UVOV Detectors Typical Waveforms
Time
V
UVOV
(V)
V
in
(V)
V
OVCOMP
V
UVCOMP
V
UVOV
While the internal current source is disabled, the UVOV
voltage is solely determined by the ratio of R1 and R2. The
input voltage at which the c onverter turns ON is given by
Equation 1. Once the i nternal current source is enabled, the
absolute value of R1 together with the ratio of R1 and R2
determine the turn OFF threshold as shown in Equa tion 2.
V
in(UV)
= V
UV
×
(R
1
+ R
2
)
R
2
(eq. 1)
V
in(OV)
= V
OV
(R
1
+ R
2
)
R
2
+ (I
offset(UVOV)
× R1)
(eq. 2)
The undervoltage threshold is trimmed during
manufacturing to obtain 3% accuracy allowing a tighter
power stage design.
Once the line voltage is within the operating range, and
V
AUX
reaches V
AUX(on)
, the outputs are enabled a nd a
soft--start sequence commences. If a UV or OV fault is
detected afterwards, the converter enters a soft--stop mode.
A small capacitor is required (>1000 pF) from the
UVOV pin to GND to prevent oscillation of the UVOV pin
and filter line transients.
Line Feedforward
The NCP1282 incorporates line feedforward (FF) to
limit the maximum volt--second product. It is the line
voltage times the ON time. This limit prevent saturation of
the transformer in forward and flyback topologies. Another
advantage of feedforward is a controller frequency gain
independent of line voltage. A constant gain facilitates
frequenc y compensation of the converter.
Feed fo rw ar d is implemented by generating a ramp
proportional to V
in
and comparing it to the error signal. The
error signal solely controls the duty cycle while the input
voltage is fixed. If the line voltage changes, the FF Ramp
slo pe chan ges and duty cycle is immediately adjus ted ins tead
of waiting for the change to propagate around the feedback
loop and be reflected back on the erro r sign al.
The FF Ramp is generated with an R --C (R
FF
C
FF
) divider
from the input line as shown in Figure 44. The di vider is
selected such that the FF Ramp reaches 3.0 V in the desired
maximum ON time. The FF Ramp terminates by
effective ly grounding C
FF
during t he converter OFF time.
This can be triggered by the FF Ramp reaching 3.0 V, or
any other condition that limits the duty cycle.
To PWM and VS
Comparators
FF Reset
I
FF(D)
V
in
R
FF
I
RFF
C
FF
FF
3V
0V
T
t
on
Figure 44. Feed Forward Ramp Generation
The FF pin is effectively grounded during power or
during standby mode to prevent the FF pin from charging
up to V
in
.
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NCP1282BDR2G

Mfr. #:
Buy NCP1282BDR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers HI PRF RSET PWM CNTR
Lifecycle:
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