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MC100LVEL13DWG

P1-P3P4-P6
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 7
1 Publication Order Number:
MC100LVEL13/D
MC100LVEL13
3.3 V ECL Dual 1:3 Fanout
Buffer
Description
The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer.
The Low Output-Output Skew of the device makes it ideal for
distributing two different frequency synchronous signals.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to V
EE
, The D input will bias
around V
CC
/2 and the Q output will go LOW.
Features
• 500 ps Typical Propagation Delays
• 50 ps Output-Output Skews
• ESD Protection: > 2 kV Human Body Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Q Output will Default LOW with Inputs Open or at V
EE
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 143 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
SOIC−20 WB
DW SUFFIX
CASE 751D
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
MARKING DIAGRAM*
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb-Free Package
20
1
100LVEL13
AWLYYWWG
Device Package
Shipping†
ORDERING INFORMATION
MC100LVEL13DWG SOIC−20 WB
(Pb-Free)
38 Units / Tube
MC100LVEL13DWR2G
1000
Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
SOIC−20 WB
(Pb-Free)
MC100LVEL13
www.onsemi.com
2
CLKa
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC
(Top View)
CLKa CLKb V
CC
1718 16 15 14 13 12
43
56789
Q2a
11
10
Q2a V
CC
Q2b Q2b Q1b Q1b V
EE
Q0a
1920
21
Q1a Q1a
V
CC
CLKbQ0a Q0b Q0b
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
Table 1. PIN DESCRIPTION
FUNCTION
ECL Differential Clock Outputs
ECL Differential Clock Outputs
ECL Differential Clock Inputs
Positive Supply
Negative Supply
PIN
Qna, Qna
Qnb, Qnb
CLKn, CLKn
V
CC
V
EE
Table 2. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6 to 0
−6 to 0
V
V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−20 WB
SOIC−20 WB
90
60
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−20 WB 30 to 35 °C/W
T
sol
Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com
3
Table 3. LVPECL DC CHARACTERISTICS (V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1))
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 30 38 30 38 32 40 mA
V
OH
Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV
V
IH
Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage (Single-Ended) 1490 1825 1490 1825 1490 1825 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
V
PP
< 500 mV
V
PP
≥ 500 mV
1.3
1.5
2.9
2.9
1.2
1.4
2.9
2.9
1.2
1.4
2.9
2.9
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current
CLKn
CLKn
0.5
−300
0.5
−300
0.5
−300
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
Table 4. LVNECL DC CHARACTERISTICS (V
CC
= 0.0 V; V
EE
= −3.3 V (Note 1))
−40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
I
EE
Power Supply Current 30 38 30 38 32 40 mA
V
OH
Output HIGH Voltage (Note 2) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV
V
OL
Output LOW Voltage (Note 2) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
V
IH
Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 −1165 −880 mV
V
IL
Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
V
PP
< 500 mV
V
PP
≥ 500 mV
−2.0
−1.8
−0.4
−0.4
−2.1
−1.9
−0.4
−0.4
−2.1
−1.9
−0.4
−0.4
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current
CLKn
CLKn
0.5
−300
0.5
−300
0.5
−300
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
P1-P3P4-P6

MC100LVEL13DWG

Mfr. #:
Buy MC100LVEL13DWG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 3.3V ECL Dual 1:3 Fanout Buffer
Lifecycle:
New from this manufacturer.
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