NJM567
-
4
-
Ver.2012-11-06
TYPICAL CHARACTERISTICS
Bandwidth Largest Detection Bandwidth
Detection Bandwidth vs. C
2
, C
3
Operating Current
Greatest Number of Cycles Output Voltage
NJM567
-
5
-
Ver.2012-11-06
DESIGN FORMULAS
mVrms200V,fof%in
Cf
V
1070
~
BW
)mV0V(
C1.07R
1
f
INO
2O
IN
IN
11
O
==
where V
IN
: Input Voltage (Vrms)
C
2
: LPF Capacitor (µF)
PLL WORDS EXPLANATIONS
Center Frequency (f
O
)
The free-running frequency of the current controlled oscillator (CCO) in the absence of an input signal.
Detection Bandwidth (BW)
The frequency range, centered about f
O
, within which an input signal above the threshold voltage (typically 20mVrms)
will cause a logical zero state on the output. The detection bandwidth corresponds to the loop capture range.
Lock Range
The largest frequency range within which an input signal above the threshold voltage will hold a logical zero state on
the output.
Detection Band Skew
A measure of how well the detection band is centered about the center frequency, f
O
. The skew is defined as (f
max
+ f
min
- 2f
O
)/ 2f
O
where f
max
and f
min
are the frequencies corresponding to the edges of the detection band. The skew can be
reduced to zero if necessary by means of an optional centering adjustment.
Operating Instructions
Figure 1 shows a typical connection diagram for the 567. For most applications, the following three-step procedure will
be sufficient for choosing the external components R
1
, C
1
C
2
and C
3
.
Figure 1
1. Select R
1
and C
1
for the desired center frequency. For best temperature stability, R
1
should be between 2K and 20K
ohm, and the combined temperature coefficient of the R
1
C
1
product should have sufficient stability over the projected
temperature range to meet the necessary requirements.
2. Select the low pass capacitor, C
2
, by referring to the Bandwidth versus Input Signal Amplitude graph. If the input
amplitude variation is known, the appropriate value of f
O
C
2
necessary to give the desired bandwidth may be found.
Conversely, an area of operation may be selected on this graph and the input level and C
2
may be adjusted accordingly.
For example, constant bandwidth operation requires that input amplitude be above 200mVrms. The bandwidth, as noted
on the graph, is then controlled solely by the f
O
C
2
product (f
O
(Hz), C
2
(µfd)).
3. The value of C
3
is generally non-critical. C
3
sets the band edge of a low pass filter which attenuates frequencies outside
the detection band to eliminate spurious outputs. If C
3
is too small, frequencies just outside the detection band will switch the
output stage on and off at the beat frequency, or the output may pulse on and off during the turn-on transient. If C
3
is too
large, turn-on and turn-off of the output stage will be delayed until the voltage on C
3
passes the threshold voltage. (Such
delay may be desirable to avoid spurious outputs due to transient frequencies.) A typical minimum value for C
3
is 2C
2
.
NJM567
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6
-
Ver.2012-11-06
Output Terminal(Fig.2)
The primary output is the uncommitted output transistor collector, pin 8. When an in-band input signal is present, this
transistor saturates; its collector voltage being less than 1.0volt (typically 0.6V) at full output current (100mA). The voltage
at pin 2 is the phase detector output which is a linear function of frequency over the range of 0.95 to 1.05 f
O
with a slope
of about 20mV per percent of frequency deviation. The average voltage at pin 1 is, during lock, a function of the inband
input amplitude in accordance with the transfer characteristic given. Pin 5 is the controlled oscillator square wave output
of magnitude (+V -2V
be
) (+V -1.4V) having a dc average of +V/2. A 1k load may be driven from pin 5. Pin 6 is an
exponential triangle of 1 volt peak-to-peak with an average dc level of +V2. Only high impedance loads may be
connected to pin 6 without affecting the CCO duty cycle or temperature stability.
Figure 2
OPERATING PRECAUTIONS
A brief review of the following precautions will help the user achieve the high level of performance of which the 567 is
capable.
1. Operation in the high level mode (above 200mV) will free the user from bandwidth variations due to changes in the
in-band signal amplitude. The input stage is now limiting, however, so that out-band signals or high noise levels can
cause an apparent bandwidth reduction as the in-band signal is suppressed. Also, the limiting action will create in-band
components from sub-harmonic signals, so the 567 becomes sensitive to signals at f
O
/ 3, f
O
/ 5, etc.
2. The 567 will lock onto signals near (2n + 1) f
O
, and will give an output for signals near (4n + 1) f
O
where n = 0, 1, 2, etc.
Thus, signals at 5f
O
and 9f
O
can cause an unwanted output. If such signals are anticipated, they should be attenuated
before reaching the 567 input.
3. Maximum immunity from noise and outband siganls is afforded in the low input level (below 200mVrms) and reduced
bandwidth operating mode. However, decreased loop damping causes the worse-case lock-up time to increase, as
shown by the Greatest Number of Cycles Before Output vs Bandwidth graph.
4. Due to the high switching speeds (20ns) associated with 567 operation, care should be taken in lead routing. Lead
lengths should be kept to a minimum. The power supply should be adequately bypassed close to the 567 with a 0.01µF
or greater capacitor; grounding paths should be carefully chosen to avoid ground loops and unwanted voltage variations.
Another factor which must be considered is the effect of load energization on the power supply. For example, an
incandescent lamp typically draws 10 times rated current at turn-on. This can cause supply voltage fluctuations which
could, for example, shift the detection band of narrow-band systems sufficiently to cause momentary loss of lock. The
result is a low-frequency oscillation into an out of lock. Such effects can be prevented by supplying heavy load currents
from a separate supply or increasing the supply filter capacitor.

NJM567D

Mfr. #:
Manufacturer:
NJR (New Japan Radio)
Description:
Phase Locked Loops - PLL Tone Decoder/Phase Locked Loop DIP-8
Lifecycle:
New from this manufacturer.
Delivery:
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