AD9949
Rev. B | Page 9 of 36
EQUIVALENT INPUT/OUTPUT CIRCUITS
R
AVDD
AVSS
AVSS
03751-004
Figure 3. CCDIN (Pin 27)
AVDD
AVSS
330
CLI
25k
1.4V
03751-005
+
Figure 4. CLI (Pin 25)
DVSS
DRVDD
DVSS DRVSS
DATA
THREE-STATE DOUT
03751-006
Figure 5. Data Outputs D0 to D11 (Pins 1 to 4, 7 to 13, 40)
03751-007
DVDD
DVSS
330
Figure 6. Digital Inputs (Pins 31 to 35, 38)
03751-008
HVDD OR RGVDD
HVSS OR RGVSS
DATA
ENABLE DOUT
Figure 7. H1 to H4 and RG (Pins 14 to 15, 18 to 19, 21)
AD9949
Rev. B | Page 10 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
03751-009
ADC OUTPUT CODE
40000 500 1000 1500 2000 2500 3000 3500
DNL (LSB)
1.0
0.5
0
–0.5
–1.0
Figure 8. Typical DNL
03751-010
VGA GAIN CODE (LSB)
10000 200 400 600 800
OUTPUT NOISE (LSB)
48
40
32
24
16
8
0
Figure 9. Output Noise vs. VGA Gain
03751-011
SAMPLE RATE (MHz)
3618 24 30
POWER DISSIPATION (mW)
400
350
300
250
200
150
V
DD
= 3.3V
V
DD
= 3.0V
V
DD
= 2.7V
Figure 10. Power Curves
AD9949
Rev. B | Page 11 of 36
SYSTEM OVERVIEW
CCD
SERIAL
INTERFACE
DOUT
DIGITAL IMAGE
PROCESSING
ASIC
V-DRIVER
HD, VD
CLI
V1 TO Vx, VSG1 TO VSGx, SUBCK
H1 TO H4, RG
CCDIN
AD9949
INTEGRATED
AFE + TD
03751-012
Figure 11. Typical Application
Figure 11 shows the typical system application diagram for the
AD9949. The CCD output is processed by the AD9949’s AFE
circuitry, which consists of a CDS, a PxGA, a VGA, a black level
clamp, and an ADC. The digitized pixel information is sent to
the digital image processor chip where all postprocessing and
compression occurs. To operate the CCD, CCD timing
parameters are programmed into the AD9949 from the image
processor through the 3-wire serial interface. From the system
master clock, CLI, provided by the image processor, the
AD9949 generates the high speed CCD clocks and all internal
AFE clocks. All AD9949 clocks are synchronized with VD and
HD. The AD9949’s horizontal pulses (CLPOB, PBLK, and
HBLK) are programmed and generated internally.
The H-drivers for H1 to H4 and RG are included in the
AD9949, allowing these clocks to be directly connected to the
CCD. The H-drive voltage of 3 V is supported in the AD9949.
Figure 12 shows the horizontal and vertical counter dimensions
for the AD9949. All internal horizontal clocking is programmed
using these dimensions to specify line and pixel locations.
H-COUNTER BEHAVIOR
When the maximum horizontal count of 4096 pixels is
exceeded, the H-counter in the AD9949 rolls over to zero and
continues counting. It is, therefore, recommended that the
maximum counter value not be exceeded.
However, the newer AD9949A version behaves differently. In
the AD9949A, the internal H-counter holds at its maximum
count of 4095 instead of rolling over. This feature allows the
AD9949A to be used in applications containing a line length
greater than 4096 pixels. Although no programmable values for
the horizontal blanking or clamping are available beyond pixel
4095, the H, RG, and AFE clocking continues to operate,
sampling the remaining pixels on the line.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
03751-013
Figure 12. Vertical and Horizontal Counters
VD
HD
CLI
MAX HD LENGTH IS 4095 PIXELS
03751-014
MAX VD LENGTH IS 4095 LINES
Figure 13. Maximum VD/HD Dimensions

AD9949AKCPZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 12-Bit CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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