MPC9448
TIMING SOLUTIONS 7 MOTOROLA
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines, the
situation in Figure 6 “Optimized Dual Line Termination”
should be used. In this case, the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is
perfectly matched.
Figure 6. Optimized Dual Line Termination
17
MPC9448
OUTPUT
BUFFER
R
S
= 16
Z
O
= 50
R
S
= 16
Z
O
= 50
17 + 16 16 = 50 50
25 = 25
Power Consumption of the MPC9448 and Thermal
Management
The MPC9448 AC specification is guaranteed for the
entire operating frequency range up to 350 MHz. The
MPC9448 power consumption and the associated long-term
reliability may decrease the maximum frequency limit,
depending on operating conditions such as clock frequency,
supply voltage, output loading, ambient temperture, vertical
convection and thermal conductivity of package and board.
This section describes the impact of these parameters on the
junction temperature and gives a guideline to estimate the
MPC9448 die junction temperature and the associated
device reliability. For a complete analysis of power
consumption as a function of operating conditions and
associated long term device reliability please refer to the
application note AN1545. According the AN1545, the
long-term device reliability is a function of the die junction
temperature:
Table 9. Die junction temperature and MTBF
Junction temperature (°C) MTBF (Years)
100 20.4
110 9.1
120 4.2
130 2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable MTBF,
the die junction temperature of the MPC9448 needs to be
controlled and the thermal impedance of the board/package
should be optimized. The power dissipated in the MPC9448
is represented in equation 1.
Where I
CCQ
is the static current consumption of the
MPC9448, C
PD
is the power dissipation capacitance per
output,
(Μ)ΣC
L
represents the external capacitive output
load, N is the number of active outputs (N is always 12 in
case of the MPC9448). The MPC9448 supports driving
transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the lumped
capacitive load at the end of the board trace, therefore,
ΣC
L
is
zero for controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination output
termination results in equation 2 for power dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, V
OL
, I
OL
, V
OH
and I
OH
are a
function of the output termination technique and DC
Q
is the
clock signal duty cyle. If transmission lines are used
ΣC
L
is
zero in equation 2 and can be eliminated. In general, the use
of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and
greatly reduces the power dissipation of the device. Equation
3 describes the die junction temperature T
J
as a function of
the power consumption.
Where R
thja
is the thermal impedance of the package
(junction to ambient) and T
A
is the ambient temperature.
According to Table 9, the junction temperature can be used to
estimate the long-term device reliability. Further, combining
equation 1 and equation 2 results in a maximum operating
frequency for the MPC9448 in a series terminated
transmission line system, equation 4.
P
TOT
I
CCQ
V
CC
f
CLOCK
N C
PD
M
C
L
V
CC
Equation 1
P
TOT
V
CC
I
CCQ
V
CC
f
CLOCK
N C
PD
M
C
L
P
DC
Q
I
OH
V
CC
V
OH
1 DC
Q
I
OL
V
OL
Equation 2
T
J
T
A
P
TOT
R
thja
Equation 3
f
CLOCK,MAX
1
C
PD
N V
2
CC
T
J,MAX
T
A
R
thja
I
CCQ
V
CC
Equation 4
MPC9448
MOTOROLA TIMING SOLUTIONS8
T
J,MAX
should be selected according to the MTBF system
requirements and Table 9. R
thja
can be derived from Table 10.
The R
thja
represent data based on 1S2P boards, using 2S2P
boards will result in a lower thermal impedance than
indicated below.
Table 10. Thermal package impedance of the 32LQFP
Convection, LFPM R
thja
(1P2S
board), °C/W
R
thja
(2P2S
board), °C/W
Still air 86 61
100 lfpm 76 56
200 lfpm 71 54
300 lfpm 68 53
400 lfpm 66 52
500 lfpm 60 49
If the calculated maximum frequency is below 350 MHz, it
becomes the upper clock speed limit for the given application
conditions. The following eight derating charts describe the
safe frequency operation range for the MPC9448. The charts
were calculated for a maximum tolerable die junction
temperature of 110°C (120°C), corresponding to an
estimated MTBF of 9.1 years (4 years), a supply voltage of
3.3V and series terminated transmission line or capacitive
loading. Depending on a given set of these operating
conditions and the available device convection a decision on
the maximum operating frequency can be made.
Figure 7. Maximum MPC9448 frequency, V
CC
= 3.3V, MTBF
9.1 years, driving series terminated transmission lines,
2s2p board
Figure 8. Maximum MPC9448 frequency, V
CC
= 3.3V,
MTBF 9.1 years, 4 pF load per line, 2s2p board
Figure 9. No maximum frequency limitation for V
CC
= 3.3V,
MTBF 4 years, driving series terminated transmission
lines, 2s2p board
Figure 10. Maximum MPC9448 frequency, V
CC
=
3.3V, MTBF 4 years, 4 pF load per line, 2s2p board
MPC9448
TIMING SOLUTIONS 9 MOTOROLA
The Following Figures Illustrate the Measurement Reference for the MPC9448 Clock Driver Circuit
Figure 11. CCLK MPC9448 AC Test Reference for V
cc
= 3.3V and V
cc
= 2.5V
Figure 12. PCLK MPC9448 AC Test Reference
Pulse
Generator
Z = 50
R
T
= 50
Z
O
= 50
R
T
= 50
Z
O
= 50
MPC9448 DUT
V
TT
V
TT
Differential
Pulse Generator
Z = 50
R
T
= 50
Z
O
= 50
R
T
= 50
Z
O
= 50
MPC9448 DUT
V
TT
V
TT

MPC9448AC

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL 1-12 LVCMOS Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet