74LVQ240SJ

© 2001 Fairchild Semiconductor Corporation DS011611 www.fairchildsemi.com
June 1993
Revised June 2001
74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
74LVQ240
Low Voltage Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The LVQ240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density.
Features
Ideal for low power/low noise 3.3V applications
Implements patented EMI reduction circuitry
Available in SOIC JEDEC, SOIC EIAJ, and QSOP pack-
ages
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Improved latch-up immunity
Guaranteed incident wave switching into 75
4 kV minimum ESD immunity
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Truth Tables
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial Z = High Impedance
Order Number Package Number Package Description
74LVQ240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVQ240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVQ240QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Pin Names Description
OE
1
, OE
2
3-STATE Output Enable Inputs
I
0
I
7
Inputs
O
0
O
7
Outputs
Inputs Outputs
OE
1
I
n
(Pins 12, 14, 16, 18)
LL H
LH L
HX Z
Inputs Outputs
OE
2
I
n
(Pins 3, 5, 7, 9)
LL H
LH L
HX Z
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74LVQ240
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
(Note 2)
Note 1: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75 for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V. One output @ GND.
Note 8: Max number of Data Inputs (n) switching. n1 Inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f = 1 MHz.
Supply Voltage (V
CC
) 0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= 0.5V 20 mA
V
I
= V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) 0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= 0.5V 20 mA
V
O
= V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) 0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
) ±400 mA
Storage Temperature (T
STG
) 65°C to +150°C
DC Latch-Up Source or
Sink Current ±300 mA
Supply Voltage (V
CC
) 2.0V to 3.6V
Input Voltage (V
I
) 0V to V
CC
Output Voltage (V
O
) 0V to V
CC
Operating Temperature (T
A
) 40°C to +85°C
Minimum Input Edge Rate (
V/t)
V
IN
0.8V to 2.0V
V
CC
@ 3.0V 125 mV/ns
Symbol Parameter
V
CC
T
A
= +25°CT
A
= 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum High Level
3.0 1.5 2.0 2.0 V
V
OUT
= 0.1V
Input Voltage or V
CC
0.1V
V
IL
Maximum Low Level
3.0 1.5 0.8 0.8 V
V
OUT
= 0.1V
Input Voltage or V
CC
0.1V
V
OH
Minimum High Level 3.0 2.99 2.9 2.9 V I
OUT
= 50 µA
Output Voltage
3.0 2.58 2.48 V
V
IN
= V
IL
or V
IH
(Note 3)
I
OH
= 12 mA
V
OL
Maximum Low Level 3.0 0.002 0.1 0.1 V I
OUT
= 50 µA
Output Voltage
3.0 0.36 0.44 V
V
IN
= V
IL
or V
IH
(Note 3)
I
OL
= 12 mA
I
IN
Maximum Input Leakage Current 3.6 ±0.1 ±1.0 µAV
I
= V
CC
, GND
I
OLD
Minimum Dynamic 3.6 36 mA V
OLD
= 0.8V Max (Note 5)
I
OHD
Output Current (Note 4) 3.6 25 mA V
OHD
= 2.0V Min (Note 5)
I
CC
Maximum Quiescent
3.6 4.0 40.0 µA
V
IN
= V
CC
Supply Current or GND
I
OZ
Maximum 3-STATE
3.6 ±0.25 ±2.5 µA
V
I
(OE) = V
IL
, V
IH
Leakage Current V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLP
Quiet Output
Maximum Dynamic V
OL
3.3 0.4 0.8 V (Note 6)(Note 7)
V
OLV
Quiet Output
Minimum Dynamic V
OL
3.3 0.4 0.8 V (Note 6)(Note 7)
V
IHD
Maximum High Level
Dynamic Input Voltage
3.3 1.6 2.0 V (Note 6)(Note 8)
V
ILD
Maximum Low Level
Dynamic Input Voltage
3.3 1.6 0.8 V (Note 6)(Note 8)
3 www.fairchildsemi.com
74LVQ240
AC Electrical Characteristics
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Note 10: C
PD
is measured at 10 MHz.
Symbol Parameter
T
A
= +25°CT
A
= 40°C to +85°C
UnitsV
CC
C
L
= 50 pF C
L
= 50 pF
(V) Min Typ Max Min Max
t
PHL
Propagation Delay 2.7 2.0 8.4 14.0 2.0 15.0
ns
t
PLH
Data to Output 3.3 ± 0.3 2.0 7.0 10.0 2.0 10.5
t
PZL
Output Enable Time 2.7 2.5 9.6 16.9 2.5 18.0
ns
t
PZH
3.3± 0.3 2.5 8.0 12.0 2.5 12.5
t
PHZ
Output Disable Time 2.7 1.0 10.2 19.0 1.0 20.0
ns
t
PLZ
3.3 ± 0.3 1.0 8.5 13.5 1.0 14.0
t
OSHL
Output to Output Skew 2.7 1.0 1.5 1.5
ns
t
OSLH
Data to Output (Note 9) 3.3 ± 0.3 1.0 1.5 1.5
Symbol Parameter Typ Units Conditions
C
IN
Input Capacitance 4.5 pF V
CC
= Open
C
PD
(Note 10) Power Dissipation Capacitance 70 pF V
CC
= 3.3V

74LVQ240SJ

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC BUFFER INVERT 3.6V 20SOP
Lifecycle:
New from this manufacturer.
Delivery:
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