LTC3446
16
3446ff
applicaTions inForMaTion
VLDO LINEAR REGULATOR DESIGN
Adjustable Output Voltage
Each VLDO regulator’s output voltage is set by the ratio
of two external resistors as shown in Figure 2. The VLDO
regulator servos the output to maintain the LV
FB
pin voltage
at 0.4V (referenced to ground). Thus the current in R1 is
equal to 0.4V/R1. For good transient response, stability and
accuracy, the current in R1 should be at least 8µA, thus
the value of R1 should be no greater than 50k. The current
in R2 is the current in R1 plus the LV
FB
pin bias current.
Since the LV
FB
pin bias current is typically <10nA, it can
be ignored in the output voltage calculation. The output
voltage can be calculated using the formula in Figure 2.
Note that in shutdown, the output is turned off and the
divider current will be zero once C
OUT
is discharged.
Each VLDO regulator operates at a relatively high gain of
–0.7µV/mA referred to its LV
FB
input. Thus a load current
change of 1mA to 300mA produces a –0.2mV drop at the
LV
FB
input. To calculate the change referred to the output,
simply multiply by the gain of the feedback network (i.e.,
1 + R2/R1). For example, to program the output for 1.2V,
choose R2/R1 = 2. In this example, an output current
change of 1mA to 300mA produces –0.2mV • (1 + 2) =
0.6mV drop at the output.
Because the LV
FB
pins are relatively high impedance (de-
pending on the resistor dividers used), stray capacitance
at these pins should be minimized (<10pF) to prevent
phase shift in the error amplifier loop. Additionally, special
attention should be given to any stray capacitances that
can couple external signals onto the LV
FB
pins producing
undesirable output ripple. For optimum performance,
connect each LV
FB
pin to its resistor divider with a short
PCB trace and minimize all other stray capacitance to the
LV
FB
pin.
VLDO Regulator Output Capacitance and Transient
Response
The VLDO regulators are designed to be stable with a
wide range of ceramic output capacitors. The ESR of the
output capacitor affects stability, most notably with small
capacitors. A minimum output capacitor of 1µF with an
ESR of 0.05Ω or less is recommended to ensure stability.
The VLDO regulators are micropower devices and output
transient response will be a function of output capacitance.
Larger values of output capacitance decrease the peak
deviations and provide improved transient response for
larger load current changes. Note that bypass capacitors
used to decouple individual components powered by a
VLDO regulator will increase the effective output capaci-
tor value. High ESR tantalum and electrolytic capacitors
may be used, but a low ESR ceramic capacitor must be
in parallel at the output. There is no minimum ESR or
maximum capacitor size requirements.
Extra consideration must be given to the use of ceramic
capacitors. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior across
temperature and applied voltage. The most common di-
electrics used are Z5U, Y5V, X5R and X7R. The Z5U and
Y5V dielectrics are good for providing high capacitances
in a small package, but exhibit large voltage and tem-
perature coefficients as shown in Figures 3 and 4. When
used with a 2V regulator, a 1µF Y5V capacitor can lose as
much as 75% of its intial capacitance over the operating
temperature range. The X5R and X7R dielectrics result
Figure 2. Programming a VLDO Regulator’s Output Voltage
R2
C
OUT
3446 F02
V
OUT
= 0.4V 1+
R2
R1
R1
( )
LV
OUT
LV
FB
GND
LTC3446
