LTC3446
10
3446ff
operaTion
switch intermittently based on load demand rather than
at a constant frequency. Every switch cycle during Burst
Mode operation delivers more energy than would occur
in constant frequency operation, minimizing the switch-
ing loss per unit of energy delivered. Since the dominant
power loss at light loads is gate charge switching loss in
the power MOSFETs, operating in Burst Mode operation
can dramatically improve light load efficiency. The tradeoff
is higher output ripple than in constant frequency opera-
tion, as well as the presence of noise below the 2.25MHz
clock frequency.
If MODESEL were instead tied to V
IN
, pulse skipping mode
is selected. In this mode, the buck converter continues to
switch at a constant frequency down to very light loads
where it will eventually begin skipping pulses. Because
constant frequency operation is extended down to light
loads, low output ripple is maintained and any coupled
or radiated noise is at or higher than the clock frequency.
The tradeoff is lower efficiency compared to Burst Mode
operation.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100%, which
is known as the dropout condition. In dropout, the PMOS
switch is turned on continuously with the output voltage
equal to the input voltage minus any voltage drop across
the PMOS switch and the external inductor.
VLDO LINEAR REGULATOR OPERATION
The two micropower, VLDO (very low dropout) linear
regulators in the LTC3446 operate from input voltages as
low as 0.9V. Each VLDO regulator provides a high accuracy
output that is capable of supplying 300mA of output cur-
rent with a typical dropout voltage of only 70mV. A single
ceramic capacitor as small as 1µF is all that is required
for output bypassing. A low reference voltage of 400mV
allows the VLDO regulators to be programmed to much
lower voltages than available in common LDOs.
As shown in the Block Diagram, the V
IN
input supplies
the internal reference and biases the VLDO circuitry while
all output current comes directly from the LV
IN
input for
high efficiency regulation. The low per-VLDO quiescent
supply currents I
LVIN
= 4µA, I
VIN
= 80µA drop to I
LVIN
<
2µA, I
VIN
< 1µA in shutdown, are well-suited to battery-
powered systems.
Each VLDO includes current limit protection. The fast
transient response of the follower output stage overcomes
the traditional tradeoff between dropout voltage, quiescent
current and load transient response inherent in most LDO
regulator architectures. Overshoot detection circuitry is
included to bring the output back into regulation when
going from heavy to light output loads (“load-dump”
handling).
POWER GOOD CIRCUIT OPERATION
The LTC3446 has a built-in supply monitor. The feedback
voltage of each enabled supply is monitored by a window
comparator to determine whether it is within 8% of its
target value. If they all are, then the PGOOD pin becomes
high impedance. If no supply is enabled, or if any enabled
supply is more than 8% away from its target, then the
PGOOD pin is driven to ground by an internal open-drain
NMOS.
The PGOOD pin may be connected through a pull-up
resistor to a supply voltage of up to 5.5V, independent of
the V
IN
pin voltage.
