DS2762BE+025 Datasheet DS2762BE+, DS2762AE+, DS2762AE+025 | P19-P21

DS2762 High-Precision Li+ Battery Monitor With Alerts

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HARDWARE CONFIGURATION

Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive it at the

appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain

or tri-state output drivers. The DS2762 used an open-drain output driver as part of the bidirectional interface

circuitry shown in Figure 16. If a bidirectional pin is not available on the bus master, separate output and input pins

can be connected together.

The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the value of

this resistor should be approximately 5kW. The idle state for the 1-Wire bus is high. If, for any reason, a bus

transaction must be suspended, the bus must be left in the idle state to properly resume the transaction later. If the

bus is left low for more than 120ms, slave devices on the bus begin to interpret the low period as a reset pulse,

effectively terminating the transaction.

Figure 16. 1-Wire Bus Interface Circuitry

TRANSACTION SEQUENCE

The protocol for accessing the DS2762 through the 1-Wire port is as follows:

§ Initialization

§ Net Address Command

§ Function Command

§ Transaction/Data

The sections that follow describe each of these steps in detail.

All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the

bus master, followed by a presence pulse simultaneously transmitted by the DS2762 and any other slaves on the

bus. The presence pulse tells the bus master that one or more devices are on the bus and ready to operate. For

more details, see the 1-Wire Signaling section.

1mA

(typ)

100W

MOSFET

Rx = RECEIVE

Tx = TRANSMIT

PULLUP

(2.0V to 5.5V)

4.7kW

BUS M

STER DS2762 1-Wire PORT

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NET ADDRESS COMMANDS

Once the bus master has detected the presence of one or more slaves, it can issue one of the net address

commands described in the following paragraphs. The name of each ROM command is followed by the 8-bit

opcode for that command in square brackets. Figure 17 presents a transaction flowchart of the net address

commands.

Read Net Address [33h or 39h]. This command allows the bus master to read the DS2762’s 1-Wire net address.

This command can only be used if there is a single slave on the bus. If more than one slave is present, a data

collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The

RNAOP bit in the status register selects the opcode for this command, with RNAOP = 0 indicating 33h, and

RNAOP = 1 indicating 39h.

Match Net Address [55h]. This command allows the bus master to specifically address one DS2762 on the 1-Wire

bus. Only the addressed DS2762 responds to any subsequent function command. All other slave devices ignore

the function command and wait for a reset pulse. This command can be used with one or more slave devices on

the bus.

Skip Net Address [CCh]. This command saves time when there is only one DS2762 on the bus by allowing the

bus master to issue a function command without specifying the address of the slave. If more than one slave device

is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at

the same time.

Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the

1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three-

step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master

performs this simple three-step routine on each bit location of the net address. After one complete pass through all

64 bits, the bus master knows the address of one device. The remaining devices can then be identified on

additional iterations of the process. See Chapter 5 of the Book of DS19xx iButton

Standards for a comprehensive

discussion of a net address search, including an actual example (www.maxim-ic.com/iButtonBook

SWAP [AAh]. SWAP is a ROM level command specifically intended to aid in distributed multiplexing applications

and is described specifically with regards to power control using the 27xx series of products. The term power

control refers to the ability of the DS2762 to control the flow of power into or out the battery pack using control pins

DC and CC. The SWAP command is issued followed by the net address. The effect is to cause the addressed

device to enable power to or from the system while simultaneously (break-before-make) deselecting and powering

down (SLEEP) all other packs. This switching sequence is controlled by a timing pulse issued on the DQ line

following the net address. The falling edge of the pulse is used to disable power with the rising edge enabling

power flow by the selected device. The DS2762 recognizes a SWAP command, device address, and timing pulse

only if the SWEN bit is set.

FUNCTION COMMANDS

After successfully completing one of the net address commands, the bus master can access the features of the

DS2762 with any of the function commands described in the following paragraphs and summarized in Table 3. The

name of each function is followed by the 8-bit opcode for that command in square brackets.

Read Data [69h, XX]. This command reads data from the DS2762 starting at memory address XX. The LSb of the

data in address XX is available to be read immediately after the MSb of the address has been entered. Because

the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XX

+ 1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read

beyond address FFh, the DS2762 outputs logic 1 until a reset pulse occurs. Addresses labeled “Reserved” in the

memory map contain undefined data. The read data command can be terminated by the bus master with a reset

pulse at any bit boundary.

iButton is a registered trademark of Dallas Semiconductor.

DS2762 High-Precision Li+ Battery Monitor With Alerts

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Write Data [6Ch, XX]. This command writes data to the DS2762 starting at memory address XX. The LSb of the

data to be stored at address XX can be written immediately after the MSb of address has been entered. Because

the address is automatically incremented after the MSb of each byte is written, the LSb to be stored at address XX

+ 1 can be written immediately after the MSb to be stored at address XX. If the bus master continues to write

beyond address FFh, the DS2762 ignores the data. Writes to read-only addresses, reserved addresses and locked

EEPROM blocks are ignored. Incomplete bytes are not written. Writes to unlocked EEPROM blocks are to shadow

RAM rather than EEPROM. See the Memory section for more details.

Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 16-byte EEPROM

block containing address XX. Copy data commands that address locked blocks are ignored. While the copy data

command is executing, the EEC bit in the EEPROM register is set to 1 and writes to EEPROM addresses are

ignored. Reads and writes to non-EEPROM addresses can still occur while the copy is in progress. The copy data

command execution time, t

EEC

, is 2ms typical and starts after the last address bit is transmitted.

Recall Data [B8h, XX]. This command recalls the contents of the 16-byte EEPROM block containing address XX

to shadow RAM.

Lock [6Ah, XX]. This command locks (write-protects) the 16-byte block of EEPROM memory containing memory

address XX. The LOCK bit in the EEPROM register must be set to l before the lock command is executed. If the

LOCK bit is 0, the lock command has no effect. The lock command is permanent; a locked block can never be

written again.

Table 3. Function Commands

COMMAND FUNCTION

COMMAND

PROTOCOL

BUS STATE AFTER

COMMAND PROTOCOL

BUS DATA

Read Data

Reads data from memory

starting at address XX

69h, XX Master Rx

Up to 256 bytes of

data

Write Data

Writes data to memory

starting at address XX

6Ch, XX Master Tx

Up to 256 bytes of

data

Copy Data

Copies shadow RAM data to

EEPROM block containing

address XX

48h, XX Bus idle None

Recall Data

Recalls EEPROM block

containing address XX to

shadow RAM

B8h, XX Bus idle None

Lock

Permanently locks the block

of EEPROM

containing address XX

6Ah, XX Bus idle None

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DS2762BE+025

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DS2762BE+025

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