3
LTC699
but not serviced prior to the time-out period, the reset
pulse generator also forces RESET to active low for a mini-
mum of 140ms for every time-out period (see Figure 2).
WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low for longer than the watchdog time-
out period forces RESET low. Floating WDI disables the
Watchdog Timer. The timer resets itself with each transition
of the Watchdog Input (see Figure 2).
V
CC
: +5V supply input. The V
CC
pin should be bypassed
with a 0.1µF capacitor.
GND: Ground pin.
RESET: Open drain output for µP reset control. When V
CC
falls below the reset voltage threshold (4.65V typically),
RESET goes active low. After V
CC
returns to 5V, the reset
pulse generator forces RESET to remain active low for a
minimum of 140ms . When the watchdog timer is enabled
PI FU CTIO S
U
U
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of circuits as described herein will not infringe on existing patent rights.
SUPPLY VOLTAGE (V)
0
RESET OUTPUT VOLTAGE (V)
3
4
5
4
2
1
0
1
2
3
5
LTC699 G01
T
A
= 25°C
EXTERNAL PULLUP = 10µA
TEMPERATURE (
°
C)
–50
RESET ACTIVE TIME (ms)
216
224
232
25 75
LTC699 G02
208
200
–25 0
50 100 125
192
184
V
CC
= 5V
Reset Voltage Threshold vs
Temperature
CCHARA TERIST
ICS
UW
AT
Y
P
I
CA
LPER
F
O
R
C
E
down, the RESET signal remains active low even with V
CC
as low as 1V. This capability helps hold the microproces-
sor in stable shutdown condition. Figure 1 shows the
timing diagram of the RESET signal.
The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at V
CC
pin do not
activate the RESET output. Response time is typically
10µs. To help prevent mistriggering due to transient loads,
V
CC
pin should be bypassed with a 0.1µF capacitor with the
leads trimmed as short as possible.
Microprocessor Reset
The LTC699 uses a bandgap voltage reference and a
precision voltage comparator C1 to monitor the 5V supply
input V
CC
(see BLOCK DIAGRAM). When V
CC
falls below
the reset voltage threshold, the RESET output is forced to
active low state. The reset voltage threshold accounts for
a 5% variation on V
CC
, so the RESET output becomes
active low when V
CC
falls below 4.65V typical. On power-
up, the RESET signal is held active low for a minimum of
140ms after reset voltage threshold is reached to allow the
power supply and microprocessor to stabilize. On power-
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
RESET Output Voltage vs
Supply Voltage
Reset Active Time vs
Temperature
TEMPERATURE (
°
C)
–50
RESET VOLTAGE THRESHOLD (V)
4.64
4.65
4.66
25 75
LTC699 G03
4.63
4.62
–25 0
50 100 125
4.61
4.60
