PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 7 of 35
NXP Semiconductors
PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
6. Functional description
Refer to Figure 1 “Logic diagram of PCA9306 (positive logic).
6.1 Function table
[1] EN is controlled by the V
bias(ref)(2)
logic levels and should be at least 1 V higher than V
ref(1)
for best
translator operation.
7. Limiting values
[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
8. Recommended operating conditions
[1] V
ref(1)
V
bias(ref)(2)
1 V for best results in level shifting applications.
Table 4. Function selection (example)
H = HIGH level; L = LOW level.
Input EN
[1]
Function
H SCL1 = SCL2; SDA1 = SDA2
L disconnect
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Symbol Parameter Conditions Min Max Unit
V
ref(1)
reference voltage (1) 0.5 +6 V
V
bias(ref)(2)
reference bias voltage (2) 0.5 +6 V
V
I
input voltage 0.5
[1]
+6 V
V
I/O
voltage on an input/output pin 0.5
[1]
+6 V
I
ch
channel current (DC) - 128 mA
I
IK
input clamping current V
I
<0V - 50 mA
T
stg
storage temperature 65 +150 C
Table 6. Operating conditions
Symbol Parameter Conditions Min Max Unit
V
I/O
voltage on an input/output pin SCL1, SDA1,
SCL2, SDA2
05V
V
ref(1)
[1]
reference voltage (1) VREF1 0 5 V
V
bias(ref)(2)
[1]
reference bias voltage (2) VREF2 0 5 V
V
I(EN)
input voltage on pin EN 0 5 V
I
sw(pass)
pass switch current - 64 mA
T
amb
ambient temperature operating in free-air 40 +85 C
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 8 of 35
NXP Semiconductors
PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
9. Static characteristics
[1] All typical values are at T
amb
=25C.
[2] Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON-state resistance is determined by the lowest voltage of the two terminals.
[3] Guaranteed by design.
[4] For DC, DC1 (VSSOP8) and GD1 (XSON8U) packages only.
Table 7. Static characteristics
T
amb
=
40
C to +85
C, unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
V
IK
input clamping voltage I
I
= 18 mA; V
I(EN)
=0V - - 1.2 V
I
IH
HIGH-level input current V
I
=5V; V
I(EN)
=0V --5A
C
i(EN)
input capacitance on pin EN V
I
= 3 V or 0 V - 7.1 - pF
C
io(off)
off-state input/output capacitance SCLn, SDAn;
V
O
=3Vor0V; V
I(EN)
=0V
-46pF
C
io(on)
on-state input/output capacitance SCLn, SDAn;
V
O
=3Vor0V; V
I(EN)
=3V
- 9.3 12.5 pF
R
on
ON-state resistance
[2]
SCLn, SDAn;
V
I
=0V;I
O
=64mA
[3]
V
I(EN)
=4.5V - 2.4 5.0
V
I(EN)
=3V - 3.0 6.0
V
I(EN)
=2.3V - 3.8 8.0
V
I(EN)
= 1.5 V - 15 32
V
I(EN)
=1.5V
[4]
-3280
V
I
=2.4V; I
O
=15mA
V
I(EN)
=4.5V - 4.8 7.5
V
I(EN)
= 3 V - 46 80
V
I
=1.7V; I
O
=15mA
V
I(EN)
= 2.3 V - 40 80
PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 9 of 35
NXP Semiconductors
PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
10. Dynamic characteristics
Table 8. Dynamic characteristics (translating down)
T
amb
=
40
C to +85
C, unless otherwise specified. Values guaranteed by design.
Symbol Parameter Conditions C
L
=50pF C
L
=30pF C
L
=15pF Unit
Min Max Min Max Min Max
V
I(EN)
= 3.3 V; V
IH
=3.3V; V
IL
=0V; V
M
= 1.15 V (see Figure 10)
t
PLH
LOW to HIGH
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
02.001.200.6ns
t
PHL
HIGH to LOW
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
02.001.500.75ns
V
I(EN)
= 2.5 V; V
IH
=2.5V; V
IL
=0V; V
M
= 0.75 V (see Figure 10)
t
PLH
LOW to HIGH
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
02.001.200.6ns
t
PHL
HIGH to LOW
propagation delay
from (input) SCL2 or SDA2
to (output) SCL1 or SDA1
02.501.500.75ns
Table 9. Dynamic characteristics (translating up)
T
amb
=
40
C to +85
C, unless otherwise specified. Values guaranteed by design.
Symbol Parameter Conditions C
L
=50pF C
L
=30pF C
L
=15pF Unit
Min Max Min Max Min Max
V
I(EN)
= 3.3 V; V
IH
=2.3V; V
IL
=0V; V
TT
= 3.3 V; V
M
=1.15V; R
L
= 300 (see Figure 10)
t
PLH
LOW to HIGH
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
01.750 1.0 0 0.5ns
t
PHL
HIGH to LOW
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
02.7501.650 0.8ns
V
I(EN)
= 2.5 V; V
IH
=1.5V; V
IL
=0V; V
TT
= 2.5 V; V
M
=0.75V; R
L
= 300 (see Figure 10)
t
PLH
LOW to HIGH
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
01.750 1.0 0 0.5ns
t
PHL
HIGH to LOW
propagation delay
from (input) SCL1 or SDA1
to (output) SCL2 or SDA2
03.302.001.0ns
a. Load circuit b. Timing diagram
S1 = translating up; S2 = translating down.
C
L
includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z
o
=50; t
r
2ns; t
f
2ns.
The outputs are measured one at a time, with one transition per measurement.
Fig 10. Load circuit for outputs
002aab845
V
TT
R
L
S1
S2 (open)
C
L
from output under test
002aab846
V
IH
V
IL
V
M
V
M
input
output
V
OH
V
OL
V
M
V
M

PCA9306D,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Translation - Voltage Levels DUAL I2C/SMBUS VOLT TRANSL
Lifecycle:
New from this manufacturer.
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