NCV8501 Series
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10
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV8501 contains the microprocessor compatible
control function RESET
(Figure 14).
Figure 14. Reset and Delay Circuit Wave Forms
V
IN
V
OUT
RESET
DELAY
(V
DT
)
Threshold
DELAY
Threshold
RESET
T
d
T
d
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until V
OUT
is within 6.0% of the regulated output
voltage, or when V
OUT
drops out of regulation,and is lower
than 8.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET
output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET
signal is valid for V
OUT
as low
as 1.0 V.
ENABLE Function
The part stays in a low I
Q
sleep mode when the ENABLE
pin is held low. The part has an internal pull down if the pin
is left floating. This is intended for failure modes only. An
external connection (active pulldown, resistor, or switch) for
normal operation is recommended.
The integrity of the ENABLE pin allows it to be tied
directly to the battery line through an external resistor. It will
withstand load dump potentials in this configuration.
Figure 15. ENABLE Function
V
IN
V
OUT
GND
NCV8501
ENABLE
V
BAT
10 k
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET
output lead.
The DELAY lead provides source current (typically 2.5 mA)
to the external DELAY capacitor during the following
proceedings:
1. During Power Up (once the regulation threshold
has been verified).
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET
threshold)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
FLAG/Monitor Function
An onchip comparator is provided to perform an early
warning to the microprocessor of a possible reset signal. The
reset signal typically turns the microprocessor off
instantaneously. This can cause unpredictable results with
the microprocessor. The signal received from the FLAG
pin
will allow the microprocessor time to complete its present
task before shutting down. This function is performed by a
comparator referenced to the bandgap reference. The actual
trip point can be programmed externally using a resistor
divider to the input monitor (MON) (Figure 16). The typical
threshold is 1.20 V on the MON pin.
Figure 16. FLAG/Monitor Function
V
BAT
V
IN
MON
V
OUT
C
OUT
V
CC
I/O
RESET
mP
FLAG
RESET
GND
DELAY
NCV8501
R
ADJ
Voltage Adjust
Figure 17 shows the device setup for a user configurable
output voltage. The feedback to the V
ADJ
pin is taken from
a voltage divider referenced to the output voltage. The loop
is balanced around the Unity Gain threshold (1.28 V
typical).
Figure 17. Adjustable Output Voltage
V
OUT
V
ADJ
NCV8501
15 k
5.1 k
C
OUT
5.0 V
1.28 V
NCV8501 Series
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11
APPLICATION NOTES
Figure 18. Additional Output Current
NCV8501
V
IN
V
OUT
V
ADJ
C2
0.1 mF
V
BAT
5.0 V
MJD31C
R1
294 k
R2
100 k
C1
47 mF
>1 Amp
Adding Capability
Figure 18 shows how the adjustable version of parts can
be used with an external pass transistor for additional current
capability. The setup as shown will provide greater than 1
Amp of output current.
FLAG MONITOR
Figure 19 shows the FLAG Monitor waveforms as a result
of the circuit depicted in Figure 16. As the output voltage
falls (V
OUT
), the Monitor threshold is crossed. This causes
the voltage on the FLAG
output to go low sending a warning
signal to the microprocessor that a RESET
signal may occur
in a short period of time. T
WA RN IN G
is the time the
microprocessor has to complete the function it is currently
working on and get ready for the RESET
shutdown signal.
Figure 19. FLAG Monitor Circuit Waveform
V
OUT
MON
RESET
FLAG Monitor
Ref. Voltage
T
WARNING
FLAG
Figure 20. Test and Application Circuit Showing
Output Compensation
V
IN
V
OUT
C
OUT
**
10 mF
R
RST
RESET
C
IN
*
0.1 mF
NCV8501
*C
IN
required if regulator is located far from the power supply filter
**C
OUT
required for stability. Capacitor must operate at minimum
temperature expected
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
t
DELAY
+
ƪ
C
DELAY
(V
dt
* Reset Delay Low Voltage)
ƫ
Delay Charge Current
Example:
Using C
DELAY
= 33 nF.
Assume reset Delay Low Voltage = 0.
Use the typical value for V
dt
= 1.8 V.
Use the typical value for Delay Charge Current = 2.5 mA.
t
DELAY
+
ƪ
33 nF(1.8 * 0)
ƫ
2.5 mA
+ 23.8 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints.
The value for the output capacitor C
OUT
shown in Figure 20
should work for most applications, however it is not
necessarily the optimized solution.
NCV8501 Series
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12
UNDERSTANDING THE NCV8501 ENABLE PIN
INPUT CURRENT
Figure 21. NCV8501 Enable Function Equivalent
Circuit
VCC
GND
ENABLE
5μA
20K
1.2M
11V 7V
~3.85V
Z1 Z2
R1
R2
D1
P1
N1
1.25VZ3
D2
D3
D4
D5
Internal
power
rail
D6
Internal
reference
(max)
Z1, R1, and Z2 provide ESD and overvoltage protection.
Note that, for ENABLE pin voltages in excess of 10 V, an
external series resistor is required to limit the current into
Z1.
For ENABLE pin voltages less than +7 V, the 5 mA
(maximum value) current source dominates the input
current, as the opposing P1 base current is negligible by
comparison.
For ENABLE pin voltages between +7 V and +11 V, the
input current is given by:
5 mA + ((V
ENABLE
7) / 20 kW)
For ENABLE pin voltages in excess of 10 V (Z1
breakover voltage can be as low as 10 V), the input current
is dominated by the external series resistor. For the case
where V
ENABLE
= 12 V; R
EXT
= 10 kW, the input current can
be up to (2 V/10 kW), = 200 mA.
The ENABLE threshold is that voltage required to
achieve ~3.85 V at the base of N1, or approximately (3.85 V
2 Vbe). At +20°C, this threshold is ~2.55 V. At 40°C, it
can be as high as 3 V.
If the value of R
EXT
is increased to ~200 kW, to reduce
ENABLE input current, then the worstcase drop across
R
EXT
must be added to 3 V to determine the effective
maximum ENABLE threshold. At V
ENABLE
< 7 V, we only
need to consider the 5 mA current sink.
Max effective threshold = 3 V + (5 mA * 220 kW)
= 3 V + 1.1 V
= 4.1 V
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 22) is:
P
D(max)
+ [V
IN(max)
* V
OUT(min)
]I
OUT(max)
) V
IN(max)
I
Q
(eq. 1)
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the
application, and
I
Q
is the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
q
JA
can be calculated:
R
QJA
+
150
C *
T
A
P
D
(eq. 2)
The value of R
q
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
q
JA
s less than the calculated value in Equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR®
I
Q
Control
Features
I
OUT
I
IN
Figure 22. Single Output Regulator with Key
Performance Parameters Labeled
V
IN
V
OUT
}
Figure 23. 16 Lead SOW (Exposed Pad), qJA as a
Function of the Pad Copper Area (2 oz. Cu
Thickness), Board Material = 0.0625, G10/R4
40
70
90
100
Thermal Resistance,
Junction to Ambient, R
q
JA
, (°C/W)
0
Copper Area (mm
2
)
200 400 800
80
60
50
600

NCV8501PDW33R2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators 3.3V 150mA w/ENABLE
Lifecycle:
New from this manufacturer.
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