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AD9840AJSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
–3–
REV. 0
AD9840A
Parameter Min Typ Max Unit Notes
P
OWER CONSUMPTION 155 mW
MAXIMUM CLOCK RATE 20 MHz
CDS
Allowable CCD Reset Transient
1
500 mV See Input Waveform in Note 1
Max CCD Black Pixel Amplitude
1
200 mV
Max Input Range before Saturation
1
1.0 V p-p With 4 dB CDS Gain
Max Input Range before Saturation 1.5 V p-p With –2 dB CDS Gain
Max Input Range before Saturation 0.5 V p-p With 10 dB CDS Gain
Max Output Range 1.6 V p-p At Any CDS Gain Setting
Gain Resolution 64 Steps
Gain Range (Two’s Complement Coding) See Figure 15 for CDS Gain Curve
Min Gain (CDS Gain Register Code 32) –2 dB
Medium Gain (CDS Gain Code 63) 4 dB 4 dB is Default with CDS Gain Disabled
Max Gain (CDS Gain Code 31) 10 dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range See Figure 13 for VGA
Gain Curve
Low Gain (VGA Register Code 91) 2 dB See Page 12 for Gain Equations
Max Gain (VGA Code 1023) 36 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output
Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB
SYSTEM PERFORMANCE Specifications Include Entire Signal Chain
Gain Accuracy, VGA Code 91 to 1023 –1.0 +1.0 dB Use Equations on Page 12 to Calculate Gain
Peak Nonlinearity, 500 mV Input Signal 0.4 % 12 dB Gain Applied (4 dB CDS Gain)
Total Output Noise 0.25 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply
POWER-UP RECOVERY TIME Clocks Must Be Applied, as in Figures 8 and 9
From Fast Recovery Mode 0.1 ms
From Reference Standby Mode 1 ms
From Total Shutdown Mode 3 ms
From Power-Off Condition 15 ms
NOTES
1
Input Signal Characteristics defined as follows, with 4 dB CDS gain:
1V MAX
INPUT
SIGNAL RANGE
200mV MAX
OPTICAL
BLACK PIXEL
500mV TYP
RESET
TRANSIENT
Specifications subject to change without notice.
CCD-MODE SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= f
SHP
= f
SHD
= 40 MHz, unless otherwise noted.)
–4–
REV. 0
AD9840A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS
Parameter Min Typ Max Unit
POWER CONSUMPTION 105 mW
MAXIMUM CLOCK RATE 40 MHz
INPUT BUFFER
Gain 0dB
Max Input Range 1.0 V p-p
VGA
Max Output Range 2.0 V p-p
Gain Control Resolution 1023 Steps
Gain (Selected Using VGA Gain Register)
Min Gain 0 dB
Max Gain 36 dB
Specifications subject to change without notice.
AUX2-MODE SPECIFICATIONS
Parameter Min Typ Max Unit
POWER CONSUMPTION 105 mW
MAXIMUM CLOCK RATE 40 MHz
INPUT BUFFER (Same as AUX1-MODE)
VGA
Max Output Range 2.0 V p-p
Gain Control Resolution 512 Steps
Gain (Selected Using VGA Gain Register)
Min Gain 0 dB
Max Gain 18 dB
ACTIVE CLAMP
Clamp Level Resolution 256 Steps
Clamp Level (Measured at ADC Output)
Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB
Specification subject to change without notice.
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 40 MHz, unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 40 MHz, unless otherwise noted.)
AD9840A
–5–
REV. 0
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
CP
25 ns
DATACLK Hi/Low Pulsewidth t
ADC
10 12.5 ns
SHP Pulsewidth t
SHP
56 ns
SHD Pulsewidth t
SHD
56 ns
CLPDM Pulsewidth t
CDM
4 10 Pixels
CLPOB Pulsewidth
1
t
COB
2 20 Pixels
SHP Rising Edge to SHD Falling Edge t
S1
06 ns
SHP Rising Edge to SHD Rising Edge t
S2
10 12.5 ns
Internal Clock Delay t
ID
3.0 ns
Inhibited Clock Period t
INH
10 ns
DATA OUTPUTS
Output Delay t
OD
14.5 16 ns
Output Hold Time t
H
7.0 7.6 ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
SCK Falling Edge to SDATA Valid Read t
DV
10 ns
NOTES
1
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9840A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
(C
L
= 20 pF, f
SAMP
= 40 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 8–10.)
ABSOLUTE MAXIMUM RATINGS
With
Respect
Parameter To Min Max Unit
AVDD1, AVDD2 AVSS –0.3 +3.9 V
DVDD1, DVDD2 DVSS –0.3 +3.9 V
DRVDD DRVSS –0.3 +3.9 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V
CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V
VRT, VRB, CMLEVEL AVSS –0.3 AVDD + 0.3 V
BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature 300 °C
(10 sec)
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9840AJST –20°C to +85°C Thin Plastic ST-48
Quad Flatpack
(LQFP)
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θ
JA
= 92°C
WARNING!
ESD SENSITIVE DEVICE
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD9840AJSTZ

Mfr. #:
Buy AD9840AJSTZ
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 10-Bit 40MHz CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
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