© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 8
1 Publication Order Number:
MC14521B/D
MC14521B
24-Stage Frequency Divider
The MC14521B consists of a chain of 24 flip−flops with an input
circuit that allows three modes of operation. The input will function as a
crystal oscillator, an RC oscillator, or as an input buffer for an external
oscillator. Each flip−flop divides the frequency of the previous flip−flop
by two, consequently this part will count up to 2
24
= 16,777,216. The
count advances on the negative going edge of the clock. The outputs of
the last seven−stages are available for added flexibility.
Features
• All Stages are Resettable
• Reset Disables the RC Oscillator for Low Standby Power Drain
• RC and Crystal Oscillator Outputs Are Capable of Driving External
Loads
• Test Mode to Reduce Test Time
• V
DD
′ and V
SS
′ Pins Brought Out on Crystal Oscillator Inverter to
Allow the Connection of External Resistors for Low−Power Operation
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Parameter
Symbol Value Unit
DC Supply Voltage Range V
DD
−0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
, V
out
−0.5 to V
DD
+0.5
V
Input or Output Current (DC or Transient)
per Pin
I
in
, I
out
± 10 mA
Power Dissipation, per Package (Note 1) P
D
500 mW
Ambient Temperature Range T
A
−55 to +125 °C
Storage Temperature Range T
stg
−65 to +150 °C
Lead Temperature (8−Second Soldering) T
L
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
1
16
14521BG
AWLYWW
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC14521B
ALYWG
16
1
MC14521BCP
AWLYYWWG
1
1
1
