MC74VHC374DTR2

MC74VHC374
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS
Unit
T
A
= 40 to 85°CT
A
= 25°C
V
CC
V
Test ConditionsParameterSymbol Unit
MaxMinMaxTypMin
V
CC
V
Test ConditionsParameterSymbol
I
in
Maximum Input
Leakage Current
V
in
= 5.5V or GND 0 to 5.5 ± 0.1 ± 1.0 μA
I
OZ
Maximum
ThreeState Leakage
Current
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ± 0.25 ± 2.5 μA
I
CC
Maximum Quiescent
Supply Current
V
in
= V
CC
or GND 5.5 4.0 40.0 μA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbol Parameter Test Conditions
T
A
= 25°C T
A
= 40 to 85°C
Unit
Min Typ Max Min Max
f
max
Maximum Clock Frequency
(50% Duty Cycle)
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
80
55
130
85
70
50
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
130
85
185
120
110
75
t
PLH
,
t
PHL
Maximum Propagation Delay,
CP to Q
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
8.1
10.6
12.7
16.2
1.0
1.0
15.0
18.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
5.4
6.9
8.1
10.1
1.0
1.0
9.5
11.5
t
PZL
,
t
PZH
Output Enable Time,
OE
to Q
V
CC
= 3.3 ± 0.3V C
L
= 15pF
R
L
= 1kΩ C
L
= 50pF
7.1
9.6
11.0
14.5
1.0
1.0
13.0
16.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
R
L
= 1kΩ C
L
= 50pF
5.1
6.6
7.6
9.6
1.0
1.0
9.0
11.0
t
PLZ
,
t
PHZ
Output Disable Time,
OE
to Q
V
CC
= 3.3 ± 0.3V C
L
= 50pF
R
L
= 1kΩ
10.2 14.0 1.0 16.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
R
L
= 1kΩ
6.1 8.8 1.0 10.0
t
OSLH
,
t
OSHL
Output to Output Skew
V
CC
= 3.3 ± 0.3V C
L
= 50pF
(Note 1)
1.5 1.5 ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
(Note 1)
1.0 1.0 ns
C
in
Maximum Input Capacitance 4 10 10 pF
C
out
Maximum ThreeState Output
Capacitance (Output in
HighImpedance State)
6 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0V
pF
32
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
t
PLHn
|, t
OSHL
= |t
PHLm
t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 8 (per flipflop). C
PD
is used to determine the
noload dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
MC74VHC374
http://onsemi.com
5
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V)
Symbol
Parameter
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.6 0.9 V
V
OLV
Quiet Output Minimum Dynamic V
OL
0.6 0.9 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
TIMING REQUIREMENTS (Input t
r
= t
f
= 3.0ns)
Symbol
Parameter Test Conditions
T
A
= 25°C
T
A
= 40
to 85°C
Unit
Typ Limit Limit
t
w
Minimum Pulse Width, CP V
CC
= 3.3 ± 0.3 V
V
CC
= 5.0 ± 0.5 V
5.0
5.0
5.5
5.0
ns
t
su
Minimum Setup Time, D to CP V
CC
= 3.3 ± 0.3 V
V
CC
= 5.0 ± 0.5 V
4.5
3.0
4.5
3.0
ns
t
h
Minimum Hold Time, D to CP V
CC
= 3.3 ± 0.3 V
V
CC
= 5.0 ± 0.5 V
2.0
2.0
2.0
2.0
ns
t
r
, t
f
Maximum Input Rise and Fall Times V
CC
= 3.3 ± 0.3 V
V
CC
= 5.0 ± 0.5 V
ns
SWITCHING WAVEFORMS
Figure 3.
V
CC
GND
50% V
CC
50%
CP
t
PLH
t
PHL
Q
t
W
1/f
max
50%
50% V
CC
50% V
CC
OE
Q
t
PZL
t
PLZ
t
PZH
t
PHZ
V
CC
GND
HIGH
IMPEDANCE
V
OL
+0.3V
V
OH
-0.3V
HIGH
IMPEDANCE
50%
D
CP
V
CC
V
CC
GND
GND
VALID
t
h
t
su
50%
Q
Figure 4.
Figure 5.
MC74VHC374
http://onsemi.com
6
TEST CIRCUITS
Figure 6.
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 kΩ
Figure 7.
Figure 8. EXPANDED LOGIC DIAGRAM
D0
3
DQ
C
Q0
2
D1
4
DQ
C
Q1
5
D2
7
DQ
C
Q2
6
D3
8
DQ
C
Q3
9
D4
13
DQ
C
Q4
12
D5
14
DQ
C
Q5
15
D6
17
DQ
C
Q6
16
D7
18
DQ
C
Q7
19
CP
OE
11
1
Figure 9. INPUT EQUIVALENT CIRCUIT
INPUT

MC74VHC374DTR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 2-5.5V CMOS Octal
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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