19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync
™™
™™
™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, SCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written, one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. A total of 28 bits for the IDT72T7285, 30 bits for the
IDT72T7295, 32 bits for the IDT72T72105 and 34 bits for the IDT72T72115.
See Figure 20, Serial Loading of Programmable Flag Registers, for the timing
diagram for this mode.
Using the serial method, individual registers cannot be programmed selec-
tively. PAE and PAF can show a valid status only after the complete set of bits
(for all offset registers) has been entered. The registers can be reprogrammed
as long as the complete set of new offset bits is entered. When LD is LOW and
SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN HIGH, data can be written to FIFO memory via
D
n by toggling WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set LD LOW
and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag will
be valid until the full set of bits required to fill all the offset registers has been written.
Measuring from the rising SCLK edge that achieves the above criteria; PAF will
be valid after three more rising WCLK edges plus tPAF, PAE will be valid after
the next three rising RCLK edges plus tPAE.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
proceeds as follows: LD and WEN must be set LOW. For x72, x36 or x18 data
on the inputs Dn are written into the Empty Offset Register on the first LOW-to-
HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK,
data are written into the Full Offset Register. The third transition of WCLK writes,
once again, to the Empty Offset Register. See Figure 3, Programmable Flag
Offset Programming Sequence. See Figure 21, Parallel Loading of Program-
mable Flag Registers, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers does
not have to occur at one time. One, two or more offset registers can be written
and then by bringing LD HIGH, write operations can be redirected to the FIFO
memory. When LD is set LOW again, and WEN is LOW, the next offset register
in sequence is written to. As an alternative to holding WEN LOW and toggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling WEN.
Note that the status of a programmable flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus t
PAF, PAE will be valid after the next two rising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset register
pointer. The contents of the offset registers can be read on the Q0-Qn pins when
LD is set LOW and REN is set LOW. It is important to note that consecutive reads
of the offset registers is not permitted. The read operation must be disabled for
a minimum of one RCLK cycle in between offset register accesses. For x72, x36
and x18 output bus width, 2 read cycles are required to obtain the values of the
offset registers. Starting with the Empty Offset Registers LSB and finishing with
the Full Offset Registers MSB. See Figure 3, Programmable Flag Offset
Programming Sequence. See Figure 22, Parallel Read of Programmable
Flag Registers, for the timing diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of which
timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT FROM MARK OPERATION
The Retransmit from Mark feature allows FIFO data to be read repeatedly
starting at a user-selected position. The FIFO is first put into retransmit mode that
will ‘mark’ a beginning word and also set a pointer that will prevent ongoing FIFO
write operations from over-writing retransmit data. The retransmit data can be
read repeatedly any number of times from the ‘marked’ position. The FIFO can
be taken out of retransmit mode at any time to allow normal device operation.
The ‘mark’ position can be selected any number of times, each selection over-
writing the previous mark location. Retransmit operation is available in both IDT
standard and FWFT modes.
During IDT standard mode the FIFO is put into retransmit mode by a Low-
to-High transition on RCLK when the ‘MARK’ input is HIGH and EF is HIGH.
The rising RCLK edge ‘marks’ the data present in the FIFO output register as
the first retransmit data. The FIFO remains in retransmit mode until a rising edge
on RCLK occurs while MARK is LOW.
Once a ‘marked’ location has been set (and the device is still in retransmit
mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK
while the retransmit input (RT) is LOW. REN must be HIGH (reads disabled)
before bringing RT LOW. The device indicates the start of retransmit setup by
setting EF LOW, also preventing reads. When EF goes HIGH, retransmit setup
is complete and read operations may begin starting with the first data at the MARK
location. Since IDT standard mode is selected, every word read including the
first ‘marked’ word following a retransmit setup requires a LOW on REN (read
enabled).
Note, write operations may continue as normal during all retransmit functions,
however write operations to the ‘marked’ location will be prevented. See Figure
18, Retransmit from Mark (IDT standard mode), for the relevant timing
diagram.
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
edge when the ‘MARK’ input is HIGH and OR is LOW. The rising RCLK edge
‘marks’ the data present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a rising RCLK edge occurs while
MARK is LOW.
