CAT5259YI-00-T2 Datasheet CAT5259WI-00-T1, CAT5259YI-00-T2, CAT5259YI-50-T2 | P7-P9

CAT5259

http://onsemi.com

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The Acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

The CAT5259 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8-bit

byte.

When the CAT5259 is in a READ mode it transmits 8 bits

of data, releases the SDA line, and monitors the line for an

acknowledge. Once it receives this acknowledge, the

CAT5259 will continue to transmit data. If no acknowledge

is sent by the Master, the device terminates data transmission

and waits for a STOP condition.

WRITE OPERATIONS

In the Write mode, the Master device sends the START

condition and the slave address information to the Slave

device. After the Slave generates an acknowledge, the

Master sends the instruction byte that defines the requested

operation of CAT5259. The instruction byte consist of a

four-bit opcode followed by two register selection bits and

two pot selection bits. After receiving another acknowledge

from the Slave, the Master device transmits the data to be

written into the selected register. The CAT5259

acknowledges once more and the Master generates the

STOP condition, at which time if a non-volatile data register

is being selected, the device begins an internal programming

cycle to non-volatile memory. While this internal cycle is in

progress, the device will not respond to any request from the

Master device.

Acknowledge Polling

The disabling of the inputs can be used to take advantage

of the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write operation, the

CAT5259 initiates the internal write cycle. ACK polling can

be initiated immediately. This involves issuing the start

condition followed by the slave address. If the CAT5259 is

still busy with the write operation, no ACK will be returned.

If the CAT5259 has completed the write operation, an ACK

will be returned and the host can then proceed with the next

instruction operation.

Write Protection

The Write Protection feature allows the user to protect

against inadvertent programming of the non-volatile data

registers. If the WP

pin is tied to LOW, the data registers are

protected and become read only. Similarly, the WP

pin is

going low after start will interrupt non-volatile write to data

registers, while WP

pin going low after an internal write

cycle has started will have no effect on any write operation.

The CAT5259 will accept both slave addresses and

instructions, but the data registers are protected from

programming by the device’s failure to send an

acknowledge after data is received.

STOP

CONDITION

START

CONDITION

ADDRESS

ACK

8TH BIT

BYTE n

SCL

SDA

Figure 3. Write Cycle Timing

Figure 4. Start/Stop Condition

START CONDITION

SDA

STOP CONDITION

SCL

CAT5259

http://onsemi.com

Figure 5. Acknowledge Condition

ACKNOWLEDGE

START

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 6. Slave Address Bits

* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

A0A1A2A31010CAT5259

INSTRUCTION AND REGISTER DESCRIPTION

Slave Address Byte

The first byte sent to the CAT5259 from the

master/processor is called the Slave Address Byte. The most

significant four bits of the slave address are a device type

identifier. These bits for the CAT5259 are fixed at 0101[B]

(refer to Figure 8).

The next four bits, A3 − A0, are the internal slave address

and must match the physical device address which is defined

by the state of the A3 − A0 input pins for the CAT5259 to

successfully continue the command sequence. Only the

device which slave address matches the incoming device

address sent by the master executes the instruction. The A3

− A0 inputs can be actively driven by CMOS input signals

or tied to V

or V

Instruction Byte

The next byte sent to the CAT5259 contains the

instruction and register pointer information. The four most

significant bits used provide the instruction opcode I3 − I0.

The R1 and R0 bits point to one of the four data registers of

each associated potentiometer. The least two significant bits

point to one of four Wiper Control Registers. The format is

shown in Figure 9.

Table 12. DATA REGISTER SELECTION

Data Register Selected R1 R0

DR0 0 0

DR1 0 1

DR2 1 0

DR3 1 1

Figure 7. Write Timing

DR1 WCRDATA

BUS ACTIVITY:

MASTER

SDA LINE

SLAVE

ADDRESS

INSTRUCTION

BYTE

Fixed Variable

op code

Address

Pot1 WCR

Address

Figure 8. Identification Byte Format

ID3 ID2 ID1 ID0 A3 A2 A1 A0

0101

(MSB) (LSB)

Device Type Identifier Slave Address

ACKACKACK

CAT5259

http://onsemi.com

Figure 9. Instruction Byte Format

I3 I2 I1 I0 R1 R0 P1 P0

(MSB) (LSB)

Instruction

Data Register

WCR/Pot Selection

Opcode

Selection

WIPER CONTROL AND DATA REGISTERS

Wiper Control Register (WCR)

The CAT5259 contains four 8-bit Wiper Control

Registers, one for each potentiometer. The Wiper Control

along its resistor array. The contents of the WCR can be

altered in four ways: it may be written by the host via Write

Wiper Control Register instruction; it may be written by

transferring the contents of one of four associated Data

Registers via the XFR Data Register instruction, it can be

modified one step at a time by the Increment/decrement

instruction (see Instruction section for more details).

Finally, it is loaded with the content of its data register zero

(DR0) upon power-up.

The Wiper Control Register is a volatile register that loses

its contents when the CAT5259 is powered-down. Although

the register is automatically loaded with the value in DR0

upon power-up, this may be different from the value present

at power-down.

Data Registers (DR)

Each potentiometer has four 8-bit non-volatile Data

Registers. These can be read or written directly by the host.

Data can also be transferred between any of the four Data

Registers and the associated Wiper Control Register. Any

data changes in one of the Data Registers is a non-volatile

operation and will take a maximum of 10 ms.

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can be used

as standard memory locations for system parameters or user

preference data.

Instructions

Four of the nine instructions are three bytes in length.

These instructions are:

 Read Wiper Control Register – read the current wiper

position of the selected potentiometer in the WCR

 Write Wiper Control Register – change current wiper

position in the WCR of the selected potentiometer

 Read Data Register – read the contents of the selected

Data Register

 Write Data Register – write a new value to the

selected Data Register

Table 13. INSTRUCTION SET (Note: 1/0 = data is one or zero.)

Instruction

Instruction Set

Operation

I3 I2 I1 I0 R1 R0 WCR1/P1 WCR0/P0

Read Wiper Control

1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Control

Write Wiper Control

1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Control Register

pointed to by P1−P0

Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed

to by P1−P0 and R1−R0

Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to

by P1−P0 and R1−R0

XFR Data Register to

Wiper Control Register

1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register

pointed to by P1−P0 and R1−R0 to its

associated Wiper Control Register

XFR Wiper Control

1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Control

Gang XFR Data

Registers to Wiper

Control Registers

0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers

pointed to by R1−R0 of all four pots to their

respective Wiper Control Registers

Gang XFR Wiper Control

Registers to Data

1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Control

Registers to their respective data Registers

pointed to by R1−R0 of all four pots

Increment/Decrement

Wiper Control Register

0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control

Latch pointed to by P1−P0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

CAT5259YI-00-T2

Mfr. #:

Buy CAT5259YI-00-T2

Manufacturer:

ON Semiconductor

Description:

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

CAT5259YI-00-T2

CAT5259YI-00-T2

Products related to this Datasheet