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MC100EP35D

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2016
October, 2017 − Rev. 8
1 Publication Order Number:
MC10EP35/D
MC100EP35
3.3V / 5V ECL JK Flip‐Flop
Description
The MC100EP35 is a higher speed/low voltage version of the EL35
JK flip-flop. The J/K data enters the master portion of the flip-flop
when the clock is LOW and is transferred to the slave, and thus the
outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
The 100 Series contains temperature compensation.
Features
• 410 ps Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range:
♦ V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
• NECL Mode Operating Range:
♦ V
CC
= 0 V with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V
EE
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
K = MC100 A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package
ALYWG
G
KP35
MARKING DIAGRAMS*
1
8
www.onsemi.com
KEP35
ALYW
G
1
8
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D
.
See detailed ordering and shipping information on page 6 o
f
this data sheet.
ORDERING INFORMATION
SOIC−8 NB
D SUFFIX
CASE
751−07
TSSOP−8
DT SUFFIX
CASE
948R−02
1
8
1
8
MC100EP35
www.onsemi.com
2
1
2
3
45
6
7
8
Q
V
EE
V
CC
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
K
QCLK
RESET
J
J
K
R
Flip Flop
Table 1. PIN DESCRIPTION
PIN
CLK*
J*, K* ECL Signal Inputs
FUNCTION
ECL Clock Inputs
RESET* ECL Asynchronous Reset
Q, Q ECL Data Outputs
Table 2. TRUTH TABLE
J
L
L
H
H
X
K
L
H
L
H
X
RESET
L
L
L
L
H
CLK
Z
Z
Z
Z
X
Qn+1
Qn
L
H
Qn
L
Z = LOW to HIGH Transition
V
CC
Positive Supply
V
EE
Negative Supply
* Pins will default LOW when left open.
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC−8 NB
TSSOP−8
Level 1
Level 3
Flammability Rating
Oxygen Index: 28 to 34
UL−94 V−0 @ 0.125 in
Transistor Count 77 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100EP35
www.onsemi.com
3
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6
−6
V
I
out
Output Current Continuous
Surge
50
100
mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB 190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−8 185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W
T
sol
Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
P1-P3P4-P6P7-P8

MC100EP35D

Mfr. #:
Buy MC100EP35D
Manufacturer:
ON Semiconductor
Description:
IC FF JK TYPE SNGL 1BIT 8SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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