MAX3440E–MAX3444E
±15kV ESD-Protected, ±60V Fault-Protected,
10Mbps, Fail-Safe RS-485/J1708 Transceivers
14 ______________________________________________________________________________________
Hot-Swap Capability
Hot-Swap Inputs
Inserting circuit boards into a hot, or powered, back-
plane may cause voltage transients on DE, DE/RE, RE,
and receiver inputs A and B that can lead to data errors.
For example, upon initial circuit board insertion, the
processor undergoes a power-up sequence. During this
period, the high-impedance state of the output drivers
makes them unable to drive the MAX3440E–MAX3444E
enable inputs to a defined logic level. Meanwhile, leak-
age currents of up to 10µA from the high-impedance out-
put, or capacitively coupled noise from V
CC
or GND,
could cause an input to drift to an incorrect logic state.
To prevent such a condition from occurring, the
MAX3440E–MAX3443E feature hot-swap input circuitry
on DE, DE/RE, and RE to guard against unwanted dri-
ver activation during hot-swap situations. The
MAX3444E has hot-swap input circuitry only on RE.
When V
CC
rises, an internal pulldown (or pullup for RE)
circuit holds DE low for at least 10µs, and until the cur-
rent into DE exceeds 200µA. After the initial power-up
sequence, the pulldown circuit becomes transparent,
resetting the hot-swap tolerable input.
Hot-Swap Input Circuitry
At the driver-enable input (DE), there are two NMOS
devices, M1 and M2 (Figure 10). When V
CC
ramps from
zero, an internal 15µs timer turns on M2 and sets the
SR latch, which also turns on M1. Transistors M2, a
2mA current sink, and M1, a 100µA current sink, pull
DE to GND through a 5.6kΩ resistor. M2 pulls DE to the
disabled state against an external parasitic capaci-
tance up to 100pF that may drive DE high. After 15µs,
the timer deactivates M2 while M1 remains on, holding
DE low against three-state leakage currents that may
drive DE high. M1 remains on until an external current
source overcomes the required input current. At this
time, the SR latch resets M1 and turns off. When M1
turns off, DE reverts to a standard, high-impedance
CMOS input. Whenever V
CC
drops below 1V, the input
is reset.
A complementary circuit for RE uses two PMOS
devices to pull RE to V
CC
.
__________Applications Information
128 Transceivers on the Bus
The MAX3440E–MAX3444E transceivers 1/4-unit-load
receiver input impedance (48kΩ) allows up to 128
transceivers connected in parallel on one communica-
tion line. Connect any combination of these devices,
and/or other RS-485 devices, for a maximum of 32-unit
loads to the line.
Reduced EMI and Reflections
The MAX3440E/MAX3442E/MAX3444E are slew-rate
limited, minimizing EMI and reducing reflections
caused by improperly terminated cables. Figure 11
shows the driver output waveform and its Fourier analy-
sis of a 125kHz signal transmitted by a MAX3443E.
High-frequency harmonic components with large ampli-
tudes are evident.
Figure 12 shows the same signal displayed for a
MAX3442E transmitting under the same conditions.
Figure 12’s high-frequency harmonic components are
much lower in amplitude, compared with Figure 11’s,
and the potential for EMI is significantly reduced.
