XRA1202
4
8-BIT I2C/SMBUS GPIO EXPANDER WITH RESET REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTIONS
1.1 I
2
C-bus Interface
The I
2
C-bus interface is compliant with the Standard-mode and Fast-mode I
2
C-bus specifications. The I
2
C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
The first byte sent by an I
2
C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA1202 responds to each write with an acknowledge
(SDA driven LOW by XRA1202 for one clock cycle when SCL is HIGH). The last byte sent by an I
2
C-bus
master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See
Figures 3 - 5 below.
For complete details, see the I
2
C-bus specifications.
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE
SWA A AP
SLAVE
ADDRESS
COMMAND
BYTE
DATA
BYTE
White block: host to XRA120x
Grey block: XRA120x to host
FIGURE 5. MASTER READS FROM SLAVE
SWA AR
SLAVE
ADDRESS
COMMAND
BYTE
White block: host to XRA120x
Grey block: XRA120x to host
AS
SLAVE
ADDRESS
nDATA ANAPLAST DATA
2
