74AUP2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 11 February 2013 8 of 21
NXP Semiconductors
74AUP2G38
Low-power dual 2-input NAND gate; open drain
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
(85 C)
Max
(125 C)
C
L
= 5 pF
t
pd
propagation delay nA, nB to nY; see Figure 8
[2]
V
CC
= 0.8 V - 13.5 - - - - ns
V
CC
= 1.1 V to 1.3 V 1.9 4.6 10.4 1.8 11.4 12.6 ns
V
CC
= 1.4 V to 1.6 V 1.5 3.3 6.5 1.4 7.4 8.2 ns
V
CC
= 1.65 V to 1.95 V 1.2 2.9 5.1 1.1 5.9 6.5 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.2 3.8 0.9 4.5 4.9 ns
V
CC
= 3.0 V to 3.6 V 0.9 2.3 4.0 0.8 4.5 4.9 ns
C
L
= 10 pF
t
pd
propagation delay nA, nB to nY; see Figure 8
[2]
V
CC
= 0.8 V - 16.3 - - - - ns
V
CC
= 1.1 V to 1.3 V 2.3 5.6 12.3 2.1 13.7 15.1 ns
V
CC
= 1.4 V to 1.6 V 1.8 4.1 7.6 1.7 8.8 9.7 ns
V
CC
= 1.65 V to 1.95 V 1.6 3.8 6.1 1.4 7.1 7.8 ns
V
CC
= 2.3 V to 2.7 V 1.4 2.9 4.6 1.2 5.4 5.9 ns
V
CC
= 3.0 V to 3.6 V 1.3 3.2 5.7 1.1 6.4 7.0 ns
C
L
= 15 pF
t
pd
propagation delay nA, nB to nY; see Figure 8
[2]
V
CC
= 0.8 V - 19.0 - - - - ns
V
CC
= 1.1 V to 1.3 V 2.6 6.6 14.2 2.4 15.8 17.4 ns
V
CC
= 1.4 V to 1.6 V 2.1 4.8 8.7 1.9 10.1 11.1 ns
V
CC
= 1.65 V to 1.95 V 1.9 4.6 7.6 1.7 8.5 9.3 ns
V
CC
= 2.3 V to 2.7 V 1.6 3.6 5.6 1.5 6.3 6.9 ns
V
CC
= 3.0 V to 3.6 V 1.6 4.1 7.5 1.4 8.3 9.1 ns
C
L
= 30 pF
t
pd
propagation delay nA, nB to nY; see Figure 8
[2]
V
CC
= 0.8 V - 27.0 - - - - ns
V
CC
= 1.1 V to 1.3 V 3.6 9.5 19.5 3.2 21.8 24.0 ns
V
CC
= 1.4 V to 1.6 V 2.9 7.0 11.5 2.6 13.6 15.0 ns
V
CC
= 1.65 V to 1.95 V 2.6 7.0 12.1 2.3 13.3 14.6 ns
V
CC
= 2.3 V to 2.7 V 2.4 5.4 8.9 2.1 9.9 10.9 ns
V
CC
= 3.0 V to 3.6 V 2.3 6.5 12.7 2.1 13.9 15.3 ns