MC74LVX373DTR2

MC74LVX373
http://onsemi.com
4
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbo
l
Parameter Test Conditions
T
A
= 25°C T
A
= −40 to 85°C
Unit
Min Typ Max Min Max
t
PLH
,
t
PHL
Propagation Delay
D to O
V
CC
= 2.7 V C
L
= 15 pF
C
L
= 50 pF
7.5
10.0
14.5
18.0
1.0
1.0
17.5
21.0
ns
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
C
L
= 50 pF
5.8
8.3
9.3
12.8
1.0
1.0
11.0
14.5
t
PLH
,
t
PHL
Propagation Delay
LE to O
V
CC
= 2.7 V C
L
= 15 pF
C
L
= 50 pF
7.7
10.2
15.0
18.5
1.0
1.0
18.5
22.0
ns
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
C
L
= 50 pF
6.0
8.5
9.7
13.2
1.0
1.0
11.5
15.0
t
PZL
,
t
PZH
Output Enable Time
OE
to O
V
CC
= 2.7 V C
L
= 15 pF
R
L
= 1 kW C
L
= 50 pF
7.7
10.2
15.0
18.5
1.0
1.0
18.5
22.0
ns
V
CC
= 3.3 ± 0.3 V C
L
= 15 pF
R
L
= 1 kW C
L
= 50 pF
6.0
8.5
9.7
13.2
1.0
1.0
11.5
15.0
t
PLZ
,
t
PHZ
Output Disable Time
OE
to O
V
CC
= 2.7 V C
L
= 50 pF
R
L
= 1 kW
9.8 18.0 1.0 21.0 ns
V
CC
= 3.3 ± 0.3 V C
L
= 50 pF
R
L
= 1 kW
8.2 12.8 1.0 14.5
t
OSHL
t
OSLH
Output−to−Output Skew
(Note 1)
V
CC
= 2.7 V C
L
= 50 pF
V
CC
= 3.3 ±0.3 V C
L
= 50 pF
1.5
1.5
1.5
1.5
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
OSHL
) or LOW−to−HIGH (t
OSLH
); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbo
l
Parameter
T
A
= 25°C T
A
= −40 to 85°C
Unit
Min Typ Max Min Max
Cin Input Capacitance 4 10 10 pF
C
out
Maximum Three−State Output Capacitance 6 pF
C
PD
Power Dissipation Capacitance (Note 2) 27 pF
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/8 (per latch). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 3.3V, Measured in SOIC Package)
Symbo
l
Characteristic
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.5 0.8 V
V
OLV
Quiet Output Minimum Dynamic V
OL
−0.5 −0.8 V
V
IHD
Minimum High Level Dynamic Input Voltage 2.0 V
V
ILD
Maximum Low Level Dynamic Input Voltage 0.8 V
TIMING REQUIREMENTS (Input t
r
= t
f
= 3.0ns)
Symbo
l
Parameter Test Conditions
T
A
= 25°C T
A
= −40 to 85°C
Unit
Typ Limit Limit
t
w(h)
Minimum Pulse Width, LE V
CC
= 2.7 V
V
CC
= 3.3 ± 0.3 V
6.5
5.0
7.5
5.0
ns
t
su
Minimum Setup Time, D to LE V
CC
= 2.7V
V
CC
= 3.3 ± 0.3 V
6.0
4.0
6.0
4.0
ns
t
h
Minimum Hold Time, D to LE V
CC
= 2.7 V
V
CC
= 3.3 ± 0.3 V
1.0
1.0
1.0
1.0
ns
MC74LVX373
http://onsemi.com
5
V
CC
GND
D
O
50%
50% VCC
t
PLH
t
PHL
V
CC
GND
50%
LE
t
PLH
t
PHL
O
t
w
50% VCC
Figure 2. Figure 3.
50%
50% VCC
50% VCC
O
t
PZL
t
PLZ
t
PZH
t
PHZ
VOL +0.3V
VOL -0.3V
V
CC
GND
HIGH
IMPEDANCE
HIGH
IMPEDANCE
O
OE
50%
D
LE
V
CC
V
CC
GND
GND
VALID
t
h
t
su
50%
Figure 4. Figure 5.
SWITCHING WAVEFORMS
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 kW
TEST CIRCUITS
Figure 6. Propagation Delay Test Circuit
Figure 7. Three−State Test Circuit
ORDERING INFORMATION
Device Package Shipping
MC74LVX373DWR2G SOIC−20
(Pb−Free)
1000 Tape & Reel
MC74LVX373DTR2G TSSOP−20
(Pb−Free)
2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MC74LVX373
http://onsemi.com
6
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
DIM
A
MIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
110
1120
PIN 1
IDENT
A
B
−T−
0.100 (0.004)
C
D
G
H
SECTION N−N
K
K1
JJ1
N
N
M
F
−W−
SEATING
PLANE
−V−
−U−
S
U
M
0.10 (0.004) V
S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
--- ---
S
U0.15 (0.006) T
7.06
16X
0.36
16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

MC74LVX373DTR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC LATCH TRANSP OCT 3ST 20-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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