MICRF010YM Datasheet MICRF010YM, MICRF010YM-TR, MICRF010BM | P7-P9

Micrel MICRF010

June 2005

M9999-063005

(408) 955-1690

is desired, use crystals with lower ESR, which normally are

bigger in size, like the HC49 package. “Application Hints

35” provides additional information and recommended

sources for crystals. If using an externally applied signal, it

should be AC-coupled and limited to the operating range of

0.2V

to 1.5V

Selecting Reference Oscillator Frequency f

As with any super-heterodyne receiver, the difference

between the internal LO (local oscillator) frequency f

and

the incoming transmit frequency f

, should equal the IF

center frequency. Equation 1 may be used to compute the

appropriate f

for a given f

= f

± 0.86

315

⎛

⎝

⎜

⎞

⎠

⎟

(1)

Frequencies f

and f

are in MHz. Note that two values

of f

exist for any given f

, distinguished as “high-side

mixing” and “low-side mixing.” High-side mixing results in

an image frequency above the frequency of interest and

low-side mixing results in a frequency below. There is

generally no preference of one over the other.

After choosing one of the two acceptable values of f

, use

Equation 2 to compute the reference oscillator frequency

= 2 ×

64.5

(2)

Frequency f

is in MHz. Connect a crystal of frequency f

to REFOSC on the MICRF010. Four-decimal-place

accuracy on the frequency is generally adequate. The

following table identifies f

for some common transmit

frequencies.

Transmit Frequency (f

)

Reference Oscillator

Frequency (f

)

315.0 MHz 9.7941 MHz

390.0 MHz 12.1260 MHz

418.0 MHz 12.9966 MHz

433.92 MHz 13.4916 MHz

Table 1. Recommended Reference Oscillator Values For

Typical Transmit Frequencies (high-side mixing)

Step 2: Selecting C

Capacitor

Extraction of the DC value of the demodulated signal for

purposes of logic-level data slicing is accomplished using

the external threshold capacitor C

and the on-chip

switched capacitor “resistor” RSC, as shown in the block

diagram.

Slicing level time constant values vary somewhat with

decoder type, data pattern, and data rate, but typically

values range from 5ms to 50ms. This issue is covered in

more detail in “Application Note 22.” Optimization of the

value of C

is required to maximize range.

Selecting Capacitor C

The first step in the process is selection of a data-slicing-

level time constant. This selection is strongly dependent

upon system issues including system decode response

time and data code structure (that is, existence of data

preamble, etc.) This issue is also covered in more detail in

“Application Note 22.”

The effective resistance of R

is listed in the electrical

characteristics table as 150kΩ at 315MHz, this value

scales inversely with frequency. R

value at other

frequencies is given by equation (4), where f

is in MHz:

9.7941

150R Ω= (4)

can be calculated using equation (5) with the

knowledge of R

and τ.

(5)

Recommended τ is 5x the bit-rate.

A standard ±20% X7R ceramic capacitor for C

generally sufficient. Refer to “Application Hint 42” for C

and C

AGC

selection examples.

Step 3: Selecting C

AGC

Capacitor

The signal path has AGC (automatic gain control) to

increase input dynamic range. The attack time constant of

the AGC is set externally by the value of the CAGC

capacitor connected to the CAGC pin of the device. To

maximize system range, it is important to keep the AGC

control voltage ripple low, preferably under 10mV

once

the control voltage attains its quiescent value. For this

reason, capacitor values of at least 0.47µF are

recommended.

The AGC control voltage is carefully managed on-chip to

allow duty-cycle operation of the MICRF010. When the

device is placed into shutdown mode (SHUT pin is pulled

high), the AGC capacitor floats to retain the voltage. When

operation is resumed, only the voltage drop, due to

capacitor leakage, must be replenished. A relatively low-

leakage capacitor such as a ceramic type is recommended

Micrel MICRF010

June 2005

M9999-063005

(408) 955-1690

when the devices are used in duty-cycled operation.

To further enhance duty-cycled operation, the AGC push

and pull currents are boosted for approximately 10ms

immediately after the device is taken out of shutdown. This

compensates for AGC capacitor voltage drop and reduces

the time to restore the correct AGC voltage. The current is

boosted by a factor of 45.

Selecting CAGC Capacitor in Continuous Mode

A CAGC capacitor in the range of 0.47µF to 4.7µF is

typically recommended. Caution! If the capacitor is too

large, the AGC may react too slowly to incoming signals.

AGC settling time, from a completely discharged (zero-volt)

state is given approximately by Equation 6:

(6)

∆t = 1.333 × C

AGC

− 0.44

where:

AGC

is in µF, and ∆t is in seconds.

Selecting CAGC Capacitor in Duty-Cycle Mode

Voltage droop across the CAGC capacitor during shutdown

should be replenished as quickly as possible after the IC is

enabled. As mentioned above, the MICRF010 boosts the

push-pull current by a factor of 45 immediately after start-

up. This fixed time period is based on the reference

oscillator frequency f

. The time is 10.9ms for f

12.00MHz, and varies inversely with f

. The value of CAGC

capacitor and the duration of the shutdown time period

should be selected such that the droop can be replenished

within this 10ms period.

Polarity of the droop is unknown, meaning the AGC voltage

could droop up or down. The worst-case from a recovery

standpoint is downward droop, since the AGC pull-up

current is 1/10th magnitude of the pull-down current. The

downward droop is replenished according to the Equation

AGC

∆V

∆t

(7)

where:

I = AGC pull-up current for the initial 10ms (67.5µA)

AGC

= AGC capacitor value

∆t = drop recovery time

∆V = drop voltage

For example, if user desires ∆t = 10ms and chooses a

4.7µF CAGC, the allowable droop is about 144mV. Using

the same equation with 200nA, the worst-case pin leakage,

and assuming 1µA of capacitor leakage in the same

direction, the maximum allowable ∆t (shutdown time) is

about 0.56s for droop recovery in 10ms.

The ratio of decay-to-attack time-constant is fixed at 1:10

(that is, the attack time constant is 10 times of the decay

time constant). Generally the design value of 1:10 is

adequate for the vast majority of applications. If adjustment

is required, adding a resistor in parallel of the C

AGC

capacitor may vary the ratio. The value of the resistor must

be determined on a case-by-case basis.

Micrel MICRF010

June 2005

M9999-063005

(408) 955-1690

The Demodulator Filter Bandwidth

There is no external control to set the demodulator

bandwidth. The maximum bandwidth is 2000 hertz at 315

MHz. Maximum bandwidth scales linearly with operating

frequency. To minimize data pulse stretching, one must

calculate the “demodulator BW required” to be certain that

it does not exceed demodulator filter bandwidth of

MICRF010 at operating frequency. For “demodulator BW

required” calculation, one needs to identify the shortest

pulse within the data profile and use equation 8 below:

width-pulse shortest

65.0

Required BW rDemodulato =

(8)

Refer to the “Electrical Characteristics” for the exact filter

bandwidth at a chosen frequency.

Power Supply Bypass Capacitors

Supply bypass capacitors are strongly recommended. One

example is to use 0.1uF ceramic capacitor in parallel with

100pF ceramic capacitor for VDD.

Data Squelching

During quiet periods (no signal), the data output (DO pin)

transitions randomly with noise. Most decoders can

discriminate between this random noise and actual data.

For some systems, random transition due to noise during

quiet period is a problem. There are three possible

approaches to reduce this output noise:

1. Analog squelch to raise the demodulator threshold.

2. Digital squelch to disable the output when data is not

present.

3. Output filter to filter the (high frequency) noise

glitches on the data output pin.

The simplest solution is to perform analog squelch by

inducing a small offset, or squelch voltage, on the CTH pin

so that noise does not trigger the internal comparator,

Usually 20mV to 30mV on CTH pin is sufficient. This may

be achieved by connecting a several-meg-ohm resistor

from the CTH pin to either VSSBB or VDDBB, depending

upon the desired offset polarity. Since MICRF010’s

receiver AGC noise at the internal comparator input is

always the same (set by the AGC), the squelch-offset

requirement does not change as the local noise strength

changes from installation to installation. Introducing

squelch will reduce sensitivity and range. One should

introduce minimal offset to sufficiently quiet the output.

Typical squelch resistor values range from 10MΩ to 6.8MΩ

for low to high squelch strength.

I/O Pin Interface Circuitry

Interface circuitry for the various I/O pins of the MICRF010

are diagrammed in Figures 2 through 8. The ESD

protection diodes at all input and output pins are not

shown.

CTH Pin

~1.6V

Demodul ator

Si g n a l

VDD

VSS

PHI2

PHI2B

PHI1

PHI1 B

VSS

TG1TG2 CTH

Figure 2. CTH Pin

Figure 2 illustrates the CTH pin interface circuit. The CTH

pin is driven from a N-Channel MOSFET source-follower

with approximately 10µA of bias. Internal control signals

PHI1/PHI2 are related in a manner such that the

impedance across the transmission gates looks like a

“resistance” of approximately 150kΩ. The DC potential at

the CTH pin is approximately 1.6V

CAGC Pin

VDD

VSS

160uA

16uA

Co m p a-

rator

7uA

85uA

Ti meo ut

CA G

Figure 3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The

AGC control voltage is developed as an integrated current

into a capacitor CAGC. The attack current is nominally

1.5µA, while the decay current is a 10 times scaling of this,

approximately 15µA. Signal gain of the RF/IF strip inside

the IC diminishes as the voltage on CAGC decreases. By

simply adding a capacitor to CAGC pin, the attack/decay

time constant ratio is fixed at 10:1. Modification of the

attack/decay ratio is possible by adding resistance from the

CAGC pin to either VDDBB or VSSBB, as desired.

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across CAGC, and

improves recovery time in duty-cycled applications. To

further improve duty-cycle recovery, both push and pull

currents are increased by 45 times for approximately 10ms

after release of the SHUT pin. This allows rapid recovery of

any voltage droop on CAGC while in shutdown.

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RF Receiver (Not Recommended for New Designs)Low Power 300-440MHz High Sensitivity Receiver

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