10
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
WUU U
the N-channel MOSFET operating in continuous mode are
given by:
N-Ch P
D
=
V
IN
V
OUT
V
IN
(I
MAX
)
2
(1 +
N
)R
DS(ON)
N-Ch Duty Cycle =
V
IN
V
OUT
V
IN
where is the temperature dependency of R
DS(ON)
. Note
that there is no transition loss term in the N-channel
dissipation equation because the drain-to-source voltage
is always low when the N-channel MOSFET is turning on
or off. The remaining I
2
R losses are the greatest at high
input voltage or during a short circuit, when the N-channel
duty cycle is nearly 100%. Fortunately, low R
DS(ON)
N-channel MOSFETs are readily available which reduce
losses to the point that heat sinking is not required, even
during continuous short-circuit operation.
The Schottky diode D1 shown in Figure 1 only conducts
during the dead-time between the conduction of the two
power MOSFETs. D1’s sole purpose in life is to prevent the
body diode of the N-channel MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency (although there are no other
harmful effects if D1 is omitted). Therefore, D1 should be
selected for a forward voltage of less than 0.7V when
conducting I
MAX
.
Finally, both MOSFETs and D1 must be selected for
breakdown voltages higher than the maximum V
IN
.
C
IN
and C
OUT
Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle V
OUT
/V
IN
. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
C
IN
Required I
RMS
I
MAX
[V
OUT
(V
IN
V
OUT
)]
1/2
V
IN
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
MAX
/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. An additional 0.1µF ceramic capacitor may also be
required on V
IN
for high frequency decoupling.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). The ESR of C
OUT
must be less
than twice the value of R
SENSE
for proper operation of the
LTC1149 series:
C
OUT
Required ESR < 2R
SENSE
Optimum efficiency is obtained by making the ESR equal
to R
SENSE
. As the ESR is increased up to 2R
SENSE
, the
efficiency degrades by less than 1%. If the ESR is greater
than 2R
SENSE
, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode
operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon, Chemicon and Sprague
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR for its size, at a somewhat
higher price. Once the ESR requirement for C
OUT
has been
met, the RMS current rating generally far exceeds the
I
RIPPLE(P-P)
requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR, or RMS
current handling requirements of the application. Alumi-
num electrolytic and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. For example,
if 200µF/10V is called for in an application requiring 3mm
height, two AVX 100µF/10V (P/N TPSD 107K010) could be
used. Consult the manufacturer for other specific recom-
mendations.
At low supply voltages, a minimum value of C
OUT
is
suggested to prevent an abnormal low frequency operat-
ing mode (see Figure 4). When C
OUT
is too small, the
11
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
WUU U
Figure 5. High Efficiency Step-Down Regulator with V
OUT
> V
CC
regulator loop adapts to the current change and returns
V
OUT
to its steady state value. During this recovery time
V
OUT
can be monitored for overshoot or ringing which
would indicate a stability problem. The Pin 7 external
components shown in the Figure 1 circuit will prove
adequate compensation for most applications.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
LTC1149 Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1149 adjustable version is used with an external
resistive divider from V
OUT
to V
FB
Pin 10. The regulated
voltage is determined:
V
OUT
= 1.25
)
)
1 +
R2
R1
In applications where V
OUT
is greater than the LTC1149
internally regulated V
CC
voltage, R
SENSE
must be moved to
output ripple at low frequencies will be large enough to trip
the voltage comparator. This causes the Burst Mode
operation to be activated when the LTC1149 series would
normally be in continuous operation. The effect is most
pronounced with low values of R
SENSE
and can be
improved by operating at higher frequencies with lower
values of L. The output remains in regulation at all times.
Checking Transient Response
Switching regulators take several cycles to respond to a
step in DC (resistive) load current. When a load step
occurs, V
OUT
shifts by an amount equal to (I
LOAD
)(ESR),
where ESR is the effective series resistance of C
OUT
.
I
LOAD
also begins to charge or discharge C
OUT
until the
0.068µF
V
IN
CAP
PDRIVE
LTC1149
I
TH
C
T
PGATE
V
CC
V
CC
SHDN2
SENSE
SENSE
+
100pF
IRFZ34
0.047µF
1N4148
1N4148
V
IN
IRF9Z34
1N5819
R
SENSE
0.05
150µF
50V
1µF
0V = NORMAL
>2V = SHUTDOWN
3300pF
C
T
200pF
1k
1149 F05
GNDS
NGATE
V
FB
1000pF
100µH
R2
215k
1%
R1
25k
1%
150µF
16V
OS-CON
LOAD
V
OUT
OUTPUT
GROUND
CONNECTION
V
OUT
= 1.25
()
1 +
R2
R1
VALUES SHOWN FOR V
OUT
= 12V
+
+
+
(V
IN
– V
OUT
) VOLTAGE (V)
0
C
OUT
(µF)
600
800
1000
4
1149 F04
400
200
0
1
2
3
5
L = 50µH
R
SENSE
= 0.02
L = 25µH
R
SENSE
= 0.02
L = 50µH
R
SENSE
= 0.05
Figure 4. Minimum Suggested C
OUT
12
LTC1149
LTC1149-3.3/LTC1149-5
APPLICATIO S I FOR ATIO
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the ground side of the output to prevent the absolute
maximum voltage ratings of the sense pins from being
exceeded. This is shown in Figure 5. When the current
sense comparator is operating at 0V common mode, the
off-time increases approximately 40%, requiring the use
of a smaller timing capacitor C
T
.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100 – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1149 series circuits: 1) LTC1149 DC supply
current, 2) MOSFET gate charge current, 3) I
2
R losses and
4) P-channel transition losses.
1. The DC supply current is the current which flows into
V
IN
Pin 2 less the gate charge current. For V
IN
= 12V the
LTC1149 DC supply current is 0.6mA for no load, and
increases proportionally with load up to 2mA after the
LTC1149 series has entered continuous mode.
Because the DC supply current is drawn from V
IN
, the
resulting loss increases with input voltage. For
V
IN
= 24V, the DC bias losses are generally less than 3%
for load currents over 300mA. However, at very low
load currents the DC bias current accounts for nearly all
of the loss.
2. MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from V
IN
to ground. The
resulting dQ/dt is a current out of V
IN
which is typically
much larger than the DC supply current. In continuous
mode, I
GATECHG
= f (Q
N
+ Q
P
). The typical gate charge
for a 0.1 N-channel power MOSFET is 25nC, and for
a P-channel about twice that value. This results in
I
GATECHG
= 7.5mA in 100kHz continuous operation, for
a 5% to 10% typical mid-current loss with V
IN
= 24V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it
argues against using larger MOSFETs than necessary
to control I
2
R losses, since overkill can cost efficiency
as well as money!
3. I
2
R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continu-
ous mode all of the output current flows through L and
R
SENSE
, but is “chopped” between the P-channel and
N-channel MOSFETs. If the two MOSFETs have
approximately the same R
DS(ON)
, then the resistance of
one MOSFET can simply be summed with the resis-
tances of L and R
SENSE
to obtain I
2
R losses. For
example, if each R
DS(ON)
= 0.1, R
L
= 0.15 and
R
SENSE
= 0.05, then the total resistance is 0.3. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I
2
R losses cause the
efficiency to roll-off at high output currents.
4. Transition losses apply only to the P-channel MOSFET,
and only when operating at high input voltages (typi-
cally 24V or greater). Transition losses can be esti-
mated from:
Transition Loss 5(V
IN
)
2
(I
MAX
)(C
RSS
)(f)
For example, if V
IN
= 48V, I
MAX
= 2A, C
RSS
= 300pF (a very
large MOSFET) and f = 100kHz, the transition loss is 0.7W.
A loss of this magnitude would not only kill efficiency but
would probably require additional heat sinking for the
MOSFET! See Design Example for further guidelines on
how to select the P-channel MOSFET.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, Schottky conduction losses during dead-time, and
inductor core losses, generally account for less than 2%
total additional loss.

LTC1149CS-5#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 5V High Eff Syn Stepdn Sw Reg
Lifecycle:
New from this manufacturer.
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