13
LTC1149
LTC1149-3.3/LTC1149-5
LTC1149 Package Dissipation
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC1149 series
to be exceeded. The LTC1149 supply current is dominated
by the gate charge supply current, which is given as a
function of operating frequency in the Typical Perfor-
mance Characteristics. The LTC1149 series junction tem-
perature can be estimated by using the equations given in
Note 1 of the Electrical Characteristics. For example, the
LT1149CS is limited to less than 11mA from a 48V supply:
T
J
= 70°C + (11mA)(48V)(110°C/W)
= 128°C exceeds absolute maximum
To prevent the maximum junction temperature from being
exceeded, the Pin 2 supply current must be checked in
continuous mode when operating at the maximum V
IN
.
Design Example
As a design example, assume V
IN
= 24V, V
OUT
= 5V,
I
MAX
= 2.5A and f = 100kHz. R
SENSE
, C
T
and L can
immediately be calculated:
R
SENSE
=
)
)
100mV
2.5
= 0.039Ω
C
T
=
(7.8)(10
–5
)
100kHz
1 –
5V
24V
= 620pF
L
MIN
= (5.1)(10
5
)(0.039Ω)(620pF)(5V) = 62µH
Selection of the P-channel MOSFET involves doing calcu-
lations for different sized MOSFETs to determine the
relative loss contributions. Taking an International Recti-
fier IRF9Z34 for example, R
DS(ON)
= 0.14Ω Max,
Q
P
= 35nC and C
RSS
= 200pF (V
DS
= V
IN
/2). These values
can be used to estimate the I
2
R losses, transition losses
and gate charge supply current losses:
Est. I
2
R Loss (T
J
= 100°C) =
(5V/24V)(2.5)
2
(1 + 0.5)0.14Ω = 270mW
Est. Transition Loss =
5(24V)
2
(2.5A)(200pF)(100kHz) = 145mW
Est. Gate Charge Loss =
(100kHz)(35nC)(24V) = 85mW
APPLICATIO S I FOR ATIO
WUU U
The same calculations were repeated for a smaller device,
the Motorola MTD2955 (R
DS(ON)
= 0.3Ω) and a larger one,
the Harris RFP30P05 (R
DS(ON)
= 0.065Ω). The results are
summarized in the table.
CONDITIONS
V
IN
= 24V, V
OUT
= 5V
F = 100kHz, I
OUT
= 2.5A MTD2955 IRF9Z34 RFP30P05
Est. I
2
R Loss (100°C) 550mW 270mW 120mW
Est. Transition Loss 110mW 145mW 290mW
Est. Gate Charge Loss 60mW 85mW 240mW
Est. Total Loss 720mW 500mW 650mW
P-CHANNEL MOSFET
For this set of conditions, the midsized P-channel MOSFET
actually produces the lowest total losses at I
MAX
. The
resulting efficiency differences will be even more pro-
nounced at lower output currents. Note that only the I
2
R
and transition losses are dissipated in the MOSFET; the
gate charge supply current loss is dissipated by the
LTC1149 series.
Selection of the N-channel MOSFET is somewhat easier; it
need only be sized for the anticipated I
2
R losses at 100%
duty cycle (worst-case assumption for short circuit.) The
Siliconix Si9410, for example, has R
DS(ON)
= 0.03Ω Max
and Q
N
= 30nC. This will produce an I
2
R loss of 250mW at
100°C and a gate charge supply current loss of 75mW. As
with the P-channel device, the use of a larger MOSFET may
actually result in lower midcurrent efficiency.
C
IN
will require an RMS current rating of at least 1.25A at
temperature, and C
OUT
will require an ESR of 0.04Ω for
optimum efficiency. The output capacitor ESR require-
ment can be fulfilled by a single OS-CON or by two or more
surface mount tantalums in parallel.
Auxiliary Windings – Suppressing Burst Mode
Operation
The LTC1149 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.
Burst Mode operation can be suppressed at low output
currents with a simple external network which cancels the
