LT1468-2
7
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Typical perForMance characTerisTics
Undistorted Output Swing
vs Frequency, V
S
= ±15V
Output Impedance vs Frequency
Undistorted Output Swing
vs Frequency, V
S
= ±5V
Large-Signal Transient, A
V
= –1
Small-Signal Transient, A
V
= –1
Open-Loop Gain and Phase
vs Frequency
Gain vs Frequency, A
V
= –1
FREQUENCY (Hz)
0
GAIN (dB)
PHASE (DEG)
10
20
30
40
50
60
10k 1M 10M 100M
14682 G13
–10
100k
70
–40
–20
0
20
40
60
80
–60
100
T
A
= 25°C
A
V
= –1
R
F
= R
G
= 5.1k
C
F
= 5pF
R
L
= 2k
PHASE
GAIN
FREQUENCY (Hz)
GAIN (dB)
14682 G14
6
0
1
2
3
4
5
–4
–3
–2
–1
–5
100k 10M 100M1M
C
L
= 100pF
C
L
= 47pF
C
L
= 22pF
NO C
L
T
A
= 25°C
A
V
= –1
R
F
= R
G
= 2k
C
F
= 6.8pF
R
L
= 500Ω
FREQUENCY (Hz)
0.01
OUTPUT IMPEDANCE (Ω)
0.1
1
10
10k 1M 10M 100M
14682 G15
0.001
100k
100
V
S
= ±15V
T
A
= 25°C
A
V
= 100
A
V
= 10
A
V
= –1
FREQUENCY (kHz)
OUTPUT VOLTAGE SWING (V
P-P
)
14682 G16
30
5
10
15
20
25
0
1 100 100010
V
S
= ±15V
T
A
= 25°C
R
L
= 2k
THD<1%
A
V
= –1
FREQUENCY (kHz)
OUTPUT VOLTAGE SWING (V
P-P
)
14682 G17
10
5
4
3
2
1
6
7
8
9
0
1 100 1000 200010
V
S
= ±5V
T
A
= 25°C
R
L
= 2k
THD<1%
A
V
= –1
50ns/DIV
14682 G20
V
S
= ±15V
20mV/DIV
200ns/DIV
14682 G21
V
S
= ±15V
A
V
= –1
R
F
= R
G
= 2k
C
L
= 22pF
2V/DIV
10V
0V
Settling Time vs Output Step
SETTLING TIME (ns)
0
OUTPUT STEP (V)
10
8
4
0
–4
–8
6
2
–2
–6
–10
400 800200 600
14682 G18
1000300 700100 500 900
V
S
= ±15V
T
A
= 25°C
R
F
= R
G
= 2.5k
R
L
= 5k
C
F
= 8pF
A
V
= –1
0.1%
0.01%
150µV
0.01%
0.1%
150µV
Settling Time vs Output Step
SETTLING TIME (ns)
0
OUTPUT STEP (V)
10
8
4
0
–4
–8
6
2
–2
–6
–10
400 800200 600
14682 G19
1000300 700100 500 900
V
S
= ±15V
T
A
= 25°C
R
F
= R
G
= 1k
R
L
= 5k INTO DIODES
C
F
= 22pF
A
V
= 2
R
L
= 511Ω/30pF
0.01%
0.01%
LT1468-2
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applicaTions inForMaTion
The LT1468-2 may be inserted directly into many operational
amplifier applications improving both DC and AC perfor-
mance, provided that the nulling circuitry is removed. The
suggested nulling circuit for the LT1468-2 is shown below.
Offset Nulling
+
LT1468-2
1
5
100k
V
V
+
4
2.2µF
0.1µF
2.2µF0.1µF
7
6
3
2
14682 AI01
and minimize leakage (i.e., 1.5of leakage between an
input and a 15V supply will generate 10nA—equal to the
maximum I
B
specification.)
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close
to that of the inputs. For inverting configurations tie the
ring to ground, in noninverting connections tie the ring
to the inverting input (note the input capacitance will
increase which may require a compensating capacitor as
discussed below.)
Microvolt level error voltages can also be generated in
the external circuitry. Thermocouple effects caused by
temperature gradients across dissimilar metals at the
contacts to the inputs can exceed the inherent drift of
the amplifier. Air currents over device leads should be
minimized, package leads should be short, and the two
input leads should be as close together as possible and
maintained at the same temperature.
Make no connection to Pin 8. This pin is used for factory
trim of the inverting input current.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole that can cause peaking
or even oscillations. A feedback capacitor
of the value:
C
F
= (R
G
)(C
IN
/R
F
)
may be used to cancel the input pole and optimize dynamic
performance. For applications where the DC noise gain is
one, and a large feedback resistor is used, C
F
should be
less than or equal to one half of C
IN
. An example would
be a DAC I-to-V converter as shown on the front page of
this data sheet where the DAC can have many tens of pF
of output capacitance.
Gain of 2 Stable
The LT1468-2 is a decompensated version of the LT1468.
The precision DC performance is identical, but the internal
compensation capacitors have been reduced to a point
where the op amp needs a gain of 2 or greater in order
to be stable.
In general, for applications where the gain around the op
amp is ≥ 2, the decompensated version should be used,
because it will give the best AC performance. In applica-
tions where the gain is < 2, the unity-gain stable version
should be used.
The appropriate way to define the ‘gain’ is as the inverse
of the feedback ratio from output to differential input,
including all relevant parasitics. Moreover, as with all
feedback loops, the stability
of the loop depends on the
value
of that feedback ratio at frequencies where the total
loop-gain would cross unity. Therefore, it is possible to
have circuits in which the gain at DC is lower than the gain
at high frequency, and these circuits can be stable even
with a non unity-gain stable op amp. An example is many
current-output DAC buffer applications.
Layout and Passive Components
The LT1468 requires attention to detail in board layout
in order to maximize DC and AC performance. For best
AC results (for example fast settling time) use a ground
plane, short lead lengths, and RF-quality bypass capacitors
(0.01µF to 0.1µF) in parallel with low ESR bypass capaci-
tors (1µF to 10µF tantalum). For best DC performance, use
“star” grounding techniques, equalize input trace lengths
Nulling Input Capacitance
+
LT1468-2
14682 AI02
R
G
R
F
C
IN
C
F
V
IN
V
OUT
LT1468-2
9
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applicaTions inForMaTion
Input Considerations
Each input of the LT1468-2 is protected with a 100Ω
series resistor and back-to-back diodes across the bases
of the input devices. If the inputs can be pulled apart, the
input current should be limited to less than 10mA with
an external series resistor. Each input also has two ESD
clamp diodesone to each supply. If an input is driven
above the supply, limit the current with an external resistor
to less than 10mA.
The LT1468-2 employs bias current cancellation at the
inputs. The inverting input current is trimmed at zero
common mode voltage to minimize errors in inverting
applications such as I-to-V converters. The noninverting
input current is not trimmed and has a wider variation
and therefore a larger maximum value. As the input offset
current can be greater than either input current, the use
of balanced source resistance is NOT recommended as it
actually degrades DC accuracy and also increases noise.
The input bias currents vary with common mode voltage
as shown in the Typical Performance Characteristics. The
cancellation circuitry was not designed to track this com-
mon mode voltage because the settling time would have
been adversely affected.
The
LT1468 inputs can be driven to the negative supply
and
to within 0.5V of the positive supply without phase
reversal. As the input moves closer than 0.5V to the posi-
tive supply, the output reverses phase.
Total Input Noise
The curve of Total Noise vs Unmatched Source Resistance
in the Typical Performance Characteristics shows that
with source resistance below 1k, the voltage noise of the
amplifier dominates. In the 1k to 20k region the increase in
noise is due to the source resistance. Above 20k the input
current noise component is larger than the resistor noise.
Input Stage Protection
R1
100Ω
R2
100Ω
+IN –IN
14682 AI03
Q1 Q2

LT1468CDD-2#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 200MHz, 30V/ s 16-B Acc AV = 2 Op Amp
Lifecycle:
New from this manufacturer.
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