ASAHI KASEI [AK2301]
<MS0416-E-02> 13 2013/05
FUNCTIONAL DESCRIPTIONS
PCM CODEC
- A/D
Analog input signal is converted to 8bit PCM data. The analog signal is fed to the anti-aliasing filter
(AAF) before converting to PCM data to prevent signals around the sampling rate from folding back
into the voice band. The converted PCM data passes through the band limiting filter which Frequency
response is designated in page8, and output from the DX pin in MSB first format. It is synchronized
with rising edge of the BCLK. This PCM data is A/u-law and full scale is defined as
3.14dBm0. The analog input of 0.762Vrms is converted to a digital code of 3.14dBm0.
- D/A
Input PCM data from the DR pin is through the digital filter, which Frequency response is designated in
page8, and converted to analog signal. This analog signal is removed the high frequency element with
SMF (fc=30kHz typ) and output from the VR pin. The input PCM data is A/u-law data and
full scale is defined as 3.14dBm0. When the input signal is 3.14dBm0, the level of the analog output
signal becomes 0.762Vrms.
PCM Data Interface
The AK2301 supports the following 2 PCM data formats
- Long Frame Sync (LF)
- Short Frame Sync (SF)
PCM data is interfaced through a pin. (DX, DR).
In each case, PCM data is interfaced in MSB first format.
Selection of the interface format
The AK2301 automatically selects the Long Frame/Short frame by means of detecting the length
frame signal.
LONG FRAME (LF) / SHORT FRAME (SF)
-Automatic LF/SF detection
The AK2301 monitors the duration of the “H” level of FS and automatically selects LF or SF interface
format.
Period of FS=”H” Frame type
More than 2 BCLK cycles LF
1 BCLK cycle SF
Timing of the interface
8bit PCM data is accommodated in 1 flame (125μs) defined by 8kHz frame sync signal. Although there are
32 time-slots at maximum in 8kHz frame (when BCLK = 2.048MHz), PCM data for the AK2301 occupies the
first time-slot.
