CY2XP31ZXIT Datasheet CY2XP31ZXIT, CY2XP31ZXCT, CY2XP31ZXI | P1-P3

CY2XP31

312.5 MHz LVPECL Clock Generator

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-06385 Rev. *H Revised April 7, 2011

Features

■ One LVPECL output pair

■ Output frequency: 312.5 MHz

■ External crystal frequency: 25 MHz

■ Low RMS phase jitter at 312.5 MHz, using 25 MHz crystal

(1.875 MHz to 20 MHz): 0.3 ps (typical)

■ Pb-free 8-Pin TSSOP package

■ Supply voltage: 3.3 V or 2.5 V

■ Commercial and industrial temperature ranges

Functional Description

The CY2XP31 is a PLL (Phase Locked Loop) based high

performance clock generator. It is optimized to generate 10 Gb

Ethernet, SONET, and other high performance clock

frequencies. It also produces an output frequency that is 12.5

times the crystal frequency. It uses Cypress’s low noise VCO

technology to achieve less than 1 ps typical RMS phase jitter,

which meets both 10 Gb Ethernet and SONET jitter

requirements. The CY2XP31 has a crystal oscillator interface

input and one LVPECL output pair.

Pinouts

Figure 1. Pin Diagram – 8-Pin TSSOP

PHASE

DETECTOR

CRYSTAL

OSCILLATOR

VCO

/25

External

Crystal

XOUT

XIN

CLK

CLK#

Logic Block Diagram

XOUT

XIN OE

VSS

VDD

CLK#

VDD

CLK

Table 1. Pin Definition – 8-Pin TSSOP

Pin Number Pin Name I/O Type Description

1, 8 VDD Power 3.3 V or 2.5 V power supply. All supply current flows through pin 1

2 VSS Power Ground

3, 4 XOUT, XIN XTAL Output and Input Parallel resonant crystal interface

5 OE CMOS Input Output enable. When HIGH, the output is enabled. When LOW, the

output is high impedance

6,7 CLK#, CLK LVPECL Output Differential clock output

[+] Feedback

CY2XP31

Document #: 001-06385 Rev. *H Page 2 of 10

Frequency Table

Inputs

Output Frequency (MHz)

Crystal Frequency (MHz) PLL Multiplier Value

25 12.5 312.5

Absolute Maximum Conditions

Parameter Description Conditions Min Max Unit

Supply Voltage –0.5 4.4 V

[1]

Input Voltage, DC Relative to V

–0.5 V

+ 0.5 V

Temperature, Storage Non operating –65 150 °C

Temperature, Junction – 135 °C

ESD

HBM

ESD Protection, Human Body Model JEDEC STD 22-A114-B 2000 – V

UL–94 Flammability Rating At 1/8 in. V–0

[2]

Thermal Resistance, Junction to Ambient 0 m/s airflow 100 °C/W

1 m/s airflow 91

2.5 m/s airflow 87

Notes

1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.

2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of

copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.

Operating Conditions

Parameter Description Min Max Unit

3.3 V Supply Voltage 3.135 3.465 V

2.5 V Supply Voltage 2.375 2.625 V

Ambient Temperature, Commercial 0 70 °C

Ambient Temperature, Industrial –40 85 °C

Power-up time for all V

to reach minimum specified voltage (ensure power ramps

is monotonic)

0.05 500 ms

[+] Feedback

CY2XP31

Document #: 001-06385 Rev. *H Page 3 of 10

DC Electrical Characteristics

Parameter Description Test Conditions Min Typ Max Unit

Operating Supply Current with

Output Unterminated

= 3.465 V, OE = V

, output untermi-

nated

– – 125 mA

= 2.625 V, OE = V

, output untermi-

nated

– – 120 mA

DDT

Operating Supply Current with

Output Terminated

= 3.465 V, OE = V

, output terminated – – 150 mA

= 2.625 V, OE = V

, output terminated – – 145 mA

LVPECL Output High Voltage V

= 3.3 V or 2.5 V, R

TERM

= 50Ω to V

–

2.0 V

–1.15 – V

–0.75 V

LVPECL Output Low Voltage V

= 3.3 V or 2.5 V, R

TERM

= 50Ω to V

–

2.0 V

–2.0 – V

–1.625 V

OD1

LVPECL Peak-to-Peak Output

Voltage Swing

= 3.3 V or 2.5 V, R

TERM

= 50Ω to V

–

2.0 V

600 – 1000 mV

OD2

LVPECL Output Voltage Swing

- V

)

= 2.5 V, R

TERM

= 50Ω to V

– 1.5 V 500 – 1000 mV

OCM

LVPECL Output Common Mode

Voltage (V

+ V

)/2

= 2.5 V, R

TERM

= 50Ω to V

– 1.5 V 1.2 – – V

LVPECL Output Leakage Current Output off, OE = V

–35 – 35 μA

Input High Voltage, OE Pin 0.7*V

–V

+0.3 V

Input Low Voltage, OE Pin –0.3 – 0.3*V

Input High Current, OE Pin OE = V

––115µA

Input Low Current, OE Pin OE = V

–50 – – µA

[5]

Input Capacitance, OE Pin – 15 – pF

INX

[5]

Pin Capacitance, XIN & XOUT – 4.5 – pF

AC Electrical Characteristics

[5]

Parameter Description Conditions Min Typ Max Unit

OUT

Output Frequency – 312.5 – MHz

, T

[3]

Output Rise or Fall Time 20% to 80% of full output swing – 0.5 1.0 ns

Jitter(φ)

[6]

RMS Phase Jitter (Random) 312.5 MHz, (1.875 to 20 MHz) – 0.3 – ps

[7]

Output Duty Cycle Measured at zero crossing point 45 – 55 %

OHZ

Output Disable Time Time from falling edge on OE to stopped

outputs (Asynchronous)

– – 100 ns

Output Enable Time Time from rising edge on OE to outputs at a

valid frequency (Asynchronous)

– – 100 ns

LOCK

Startup Time Time for CLK to reach valid frequency

measured from the time

= V

(min.)

––5ms

Recommended Crystal Specifications

[4]

Parameter Description Min Max Unit

Mode Mode of Oscillation Fundamental

F Frequency 25 25 MHz

ESR Equivalent Series Resistance – 50 Ω

Shunt Capacitance – 7 pF

[+] Feedback

P1-P3 P4-P6 P7-P9 P10-P10

CY2XP31ZXIT

Mfr. #:

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Manufacturer:

Cypress Semiconductor

Description:

Clock Generators & Support Products 312.5MHz 0.3ps 125mA

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