XA Artix-7 FPGAs Data Sheet: Overview
DS197 (v1.2) February 23, 2017 www.xilinx.com
Product Specification 4
During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain
unchanged.
Programmable Data Width
Each port can be configured as 32K × 1, 16K × 2, 8K × 4, 4K × 9 (or 8), 2K × 18 (or 16), 1K × 36 (or 32), or 512 × 72 (or 64).
The two ports can have different aspect ratios without any constraints.
Each block RAM can be divided into two completely independent 18 Kb block RAMs that can each be configured to any
aspect ratio from 16K × 1 to 512 × 36. Everything described previously for the full 36 Kb block RAM also applies to each of
the smaller 18 Kb block RAMs.
Only in simple dual-port (SDP) mode can data widths of greater than 18 bits (18 Kb RAM) or 36 bits (36 Kb RAM) be
accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode, one side (read
or write) can be variable, while the other is fixed to 32/36 or 64/72.
Both sides of the dual-port 36 Kb RAM can be of variable width.
Two adjacent 36 Kb block RAMs can be configured as one cascaded 64K × 1 dual-port RAM without any additional logic.
Error Detection and Correction
Each 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error
correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or
reading from external 64- to 72-bit-wide memories.
FIFO Controller
The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments
the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and
almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the
write and read ports always have identical width.
First word fall-through mode presents the first-written word on the data output even before the first read operation. After the
first word has been read, there is no difference between this mode and the standard mode.
Digital Signal Processing — DSP Slice
Some highlights of the DSP functionality include:
• 25 × 18 two's complement multiplier/accumulator high-resolution (48 bit) signal processor
• Power saving pre-adder to optimize symmetrical filter applications
• Advanced features: optional pipelining, optional ALU, and dedicated buses for cascading
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All 7 series
FPGAs have many dedicated, full custom, low-power DSP slices, combining high speed with small size while retaining
system design flexibility.
Each DSP slice fundamentally consists of a dedicated 25 × 18 bit twos complement multiplier and a 48-bit accumulator, both
capable of operating up to 550 MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can feed a single-
instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit
add/subtract/accumulate), or a logic unit that can generate any one of ten different logic functions of the two operands.
The DSP includes an additional pre-adder, typically used in symmetrical filters. This pre-adder improves performance in
densely packed designs and reduces the DSP slice count by up to 50%. The DSP also includes a 48-bit-wide Pattern
Detector that can be used for convergent or symmetric rounding. The pattern detector is also capable of implementing
96-bit-wide logic functions when used in conjunction with the logic unit.
The DSP slice provides extensive pipelining and extension capabilities that enhance the speed and efficiency of many
applications beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide bus
multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down counter.
