Data Sheet ADuM1210
Rev. D | Page 5 of 20
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ V
DD1
≤ 3.6 V, 2.7 V ≤ V
DD2
≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.0 V. All voltages are relative to their respective ground.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel,
Quiescent
I
DDI (Q)
0.26 0.35 mA
Output Supply Current, per Channel,
Quiescent
I
DDO (Q)
0.11 0.20 mA
Total Supply Current, Two Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
0.6 1.0 mA DC to 1 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (Q)
0.2 0.6 mA DC to 1 MHz logic signal frequency
10 Mbps
V
DD1
Supply Current I
DD1 (10)
2.2 3.4 mA 5 MHz logic signal frequency
V
DD2
Supply Current I
DD2 (10)
0.7 1.1 mA 5 MHz logic signal frequency
Input Currents I
IA
, I
IB
−10 +0.01 +10 μA 0 V ≤ V
IA
, V
IB
, ≤ V
DD1
Logic High Input Threshold V
IH
0.7 × V
DD1
V
Logic Low Input Threshold V
IL
0.3 × V
DD1
V
Logic High Output Voltages V
OAH
, V
OBH
V
DD2
− 0.1 3.0 V I
Ox
= −20 μA, V
Ix
= V
IxH
V
DD2
− 0.5 2.8 V I
Ox
= −4 mA, V
Ix
= V
IxH
Logic Low Output Voltages V
OAL
, V
OBL
0.0 0.1 V I
Ox
= 20 μA, V
Ix
= V
IxL
0.04 0.1 V I
Ox
= 400 μA, V
Ix
= V
IxL
0.2 0.4 V I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 60 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
22 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
22 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
3.0 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
7
|CM
H
| 25 35 kV/μs
V
Ix
= V
DD1
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
|CM
L
| 25 35 kV/μs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.1 Mbps
Input Dynamic Supply Current,
per Channel
8
I
DDI (D)
0.10 mA/Mbps
Output Dynamic Supply Current,
per Channel
8
I
DDO (D)
0.03 mA/Mbps
1
The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See
through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See and for
total V
DD1
and V
DD2
supply currents as a function of data rate.
Power Consumption
Figure 4 Figure 6 Figure 7 Figure 8
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
