74AUP1G32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 8 July 2013 9 of 21
NXP Semiconductors
74AUP1G32
Low-power 2-input OR-gate
[1] All typical values are measured at nominal V
CC
.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
T
amb
= 25 C
C
PD
power dissipation capacitance f = 1 MHz; V
I
= GND to V
CC
[3]
V
CC
= 0.8 V - 2.5 - pF
V
CC
= 1.1 V to 1.3 V - 2.6 - pF
V
CC
= 1.4 V to 1.6 V - 2.8 - pF
V
CC
= 1.65 V to 1.95 V - 2.9 - pF
V
CC
= 2.3 V to 2.7 V - 3.4 - pF
V
CC
= 3.0 V to 3.6 V - 3.9 - pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9
Symbol Parameter Conditions Min Typ
[1]
Max Unit
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Max Min Max
C
L
= 5 pF
t
pd
propagation delay A, B to Y; see Figure 8
[1]
V
CC
= 1.1 V to 1.3 V 2.1 11.9 2.1 13.2 ns
V
CC
= 1.4 V to 1.6 V 1.4 7.5 1.4 8.3 ns
V
CC
= 1.65 V to 1.95 V 1.2 6.0 1.2 6.6 ns
V
CC
= 2.3 V to 2.7 V 1.0 4.6 1.0 5.1 ns
V
CC
= 3.0 V to 3.6 V 0.9 4.1 0.9 4.6 ns
C
L
= 10 pF
t
pd
propagation delay A, B to Y; see Figure 8
[1]
V
CC
= 1.1 V to 1.3 V 2.1 13.8 2.1 15.2 ns
V
CC
= 1.4 V to 1.6 V 1.7 8.7 1.7 9.6 ns
V
CC
= 1.65 V to 1.95 V 1.5 6.9 1.5 7.7 ns
V
CC
= 2.3 V to 2.7 V 1.3 5.5 1.3 6.1 ns
V
CC
= 3.0 V to 3.6 V 1.2 5.0 1.2 5.5 ns
