AD7887ARM-REEL7 Datasheet AD7887ARMZ, AD7887BRZ, AD7887WARMZ | P10-P12

Data Sheet AD7887

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The end-

points of the transfer function are zero scale, a point ½ LSB

below the first code transition, and full scale, a point ½ LSB

above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (00 . . . 000) to

(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.

Offset Error Match

This is the difference in offset error between any two channels.

Gain Error

This is the deviation of the last code transition (111 . . . 110) to

(111 . . . 111) from the ideal (that is, V

REF

− 1.5 LSB) after the

offset error has been adjusted out.

Gain Error Match

This is the difference in gain error between any two channels.

Track/Hold Acquisition Time

The track/hold amplifier returns to track mode at the end of

conversion. Track/hold acquisition time is the time required for

the output of the track/hold amplifier to reach its final value,

within ±1/2 LSB, after the end of a conversion.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the ADC. The signal is the rms amplitude of the fun-

damental. Noise is the sum of all nonfundamental signals up to half

the sampling frequency (f

/2), excluding dc. The ratio is dependent

on the number of quantization levels in the digitization process: the

more levels, the smaller the quantization noise. The theoretical

signal to (noise + distortion) ratio for an ideal N-bit converter

with a sine wave input is given by

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7887, it is defined as

log20)dB(

VVVVV

THD

++++

where V

is the rms amplitude of the fundamental and V

, V

, and V

are the rms amplitudes of the second through the

sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f

/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, the

largest harmonic could be a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb,

any active device with nonlinearities creates distortion products

at sum and difference frequencies of mfa ± nfb where m, n = 0,

1, 2, 3, and so on. Intermodulation distortion terms are those for

which neither m nor n are equal to 0. For example, the second-

order terms include (fa + fb) and (fa − fb), and the third order

terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb).

The AD7887 is tested using the CCIF standard in which two

input frequencies near the top end of the input bandwidth are

used. In this case, the second-order terms are usually distanced

in frequency from the original sine waves, and the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification, where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in decibels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale 25 kHz sine wave signal to the nonselected input channel

and determining how much that signal is attenuated in the

selected channel. The figure given is the worst case across both

channels for the AD7887.

Power Supply Rejection (PSR)

Variations in power supply affect the full-scale transition, but

not the converter’s linearity. PSR is the maximum change in the

full-scale transition point due to a change in power supply voltage

from the nominal value. See Figure 7.

PSRR is defined as the ratio of the power in the ADC output at

frequency f to the power of a full-scale sine wave applied to the

ADC of frequency f

PSRR (dB) = 10 log(Pf/Pfs)

where Pf is the power at frequency f in ADC output and Pfs is

the power at frequency f

in ADC full-scale input.

Rev. E | Page 9 of 24

AD7887 Data Sheet

CONTROL REGISTER

The control register on the AD7887 is an 8-bit, write-only register. Data is loaded from the DIN pin of the AD7887 on the rising edge of

SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. This requires 16 serial

clocks for every data transfer. Only the information provided on the first eight rising clock edges after

falling edge is loaded to the

control register. MSB denotes the first bit in the data stream. The bit functions are outlined in Table 5. The contents of the control register

on power up is all 0s.

MSB

DONTC ZERO REF SIN/DUAL CH ZERO PM1 PM0

Table 5. Control Register

Bit Mnemonic Comment

7 DONTC Don’t Care. The value written to this bit of the control register is a don’t care, that is, it doesn’t matter if the bit

is 0 or 1.

6 ZERO A zero must be written to this bit to ensure correct operation of the AD7887.

5 REF Reference Bit. With a 0 in this bit, the on-chip reference is enabled. With a 1 in this bit, the on-chip reference is

disabled.

4 SIN/DUAL Single/Dual Bit. This bit determines whether the AD7887 operates in single-channel or dual-channel mode. A

0 in this bit selects single-channel operation and the AIN1/V

REF

pin assumes its V

REF

function. A 1 in this bit selects

dual-channel mode, with the reference voltage for the ADC internally connected to V

and the AIN1/V

REF

assuming its AIN1 function as the second analog input channel. To obtain best performance from the AD7887,

the internal reference should be disabled when operating in the dual-channel mode, that is, REF = 1.

Channel Bit. When the part is selected for dual-channel mode, this bit determines which channel is converted

for the next conversion. A 0 in this bit selects the AIN0 input, and a 1 in this bit selects the AIN1 input. In single-

channel mode, this bit should always be 0.

2 ZERO A 0 must be written to this bit to ensure correct operation of the AD7887.

1, 0 PM1, PM0 Power Management Bits. These two bits decode the mode of operation of the AD7887 as described in Table 6.

Table 6. Power Management Options

PM1 PM0 Mode

0 0 Mode 1. In this mode, the AD7887 enters shutdown if the

input is 1 and is in full power mode when

is 0.

Thus the part comes out of shutdown on the falling edge of

and enters shutdown on the rising edge of

0 1 Mode 2. In this mode, the AD7887 is always fully powered up, regardless of the status of any of the logic inputs.

1 0 Mode 3. In this mode, the AD7887 automatically enters shutdown mode at the end of each conversion,

regardless of the state of

1 1 Mode 4. In this standby mode, portions of the AD7887 are powered down but the on-chip reference voltage

remains powered up. This mode is similar to Mode 3, but allows the part to power up much faster. The REF bit

should be 0 to ensure that the on-chip reference is enabled.

Rev. E | Page 10 of 24

Data Sheet AD7887

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7887 is a fast, low power, 12-bit, single-supply, single-

channel/dual-channel ADC. The part can be operated from a

3 V (2.7 V to 3.6 V) supply or from a 5 V (4.75 V to 5.25 V) supply.

When operated from either a 5 V or 3 V supply, the AD7887 is

capable of throughput rates of 125 kSPS when provided with a

2 MHz clock.

The AD7887 provides the user with an on-chip, track/hold

analog-to-digital converter reference and a serial interface

housed in an 8-lead package. The serial clock input accesses data

from the part and provides the clock source for the successive

approximation ADC. The part can be configured for single-

channel or dual-channel operation. When configured as a

single-channel part, the analog input range is 0 to V

REF

(where the

externally applied V

REF

can be between 1.2 V and V

). When

the AD7887 is configured for two input channels, the input

range is determined by internal connections to be 0 to V

If single-channel operation is required, the AD7887 can be

operated in a read-only mode by tying the DIN line permanently

to GND. For applications where the user wants to change the

mode of operation or wants to operate the AD7887 as a dual-

channel ADC, the DIN line can be used to clock data into the

part’s control register.

CONVERTER OPERATION

The AD7887 is a successive approximation ADC built around a

charge-redistribution DAC. Figure 8 and Figure 9 show simplified

schematics of the ADC. Figure 8 shows the ADC during its

acquisition phase. SW2 is closed and SW1 is in Position A, the

comparator is held in a balanced condition, and the sampling

capacitor acquires the signal on AIN.

(REF IN/REF OUT)/2

SAMPLING

CAPACITOR

COMPARATOR

ACQUISITION

PHASE

SW1

SW2

AGND

AIN

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

06191-008

Figure 8. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 9), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the charge-redistribution DAC

are used to add and subtract fixed amounts of charge from the

sampling capacitor to bring the comparator back into a balanced

condition. When the comparator is rebalanced, the conversion

is complete. The control logic generates the ADC output code.

Figure 10 shows the ADC transfer function.

(REF IN/REF OUT)/2

SAMPLING

CAPACITOR

COMPARATOR

CONVERSION

PHASE

SW1

SW2

AGND

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

06191-009

Figure 9. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7887 is straight binary. The

designed code transitions occur at successive integer LSB values

(that is, 1 LSB, 2 LSB, and so on). The LSB size is V

REF

/4096. The

ideal transfer characteristic for the AD7887 is shown in Figure 10.

ADC CODE

ANALOG INPUT

111 ... 000

011 ... 111

0.5LSB

REF

– 1.5LSB

1LSB = V

REF

/4096

111 ... 111

111 ... 110

000 ... 010

000 ... 001

000 ... 000

06191-010

Figure 10. Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 11 shows a typical connection diagram for the AD7887.

The GND pin is connected to the analog ground plane of the

system. The part is in dual-channel mode so V

REF

is internally

connected to a well-decoupled V

pin to provide an analog

input range of 0 V to V

. The conversion result is output in a

16-bit word with four leading zeros followed by the MSB of the

12-bit result. For applications where power consumption is of

concern, the automatic power-down at the end of conversion

should be used to improve power performance. See the Modes

of Operation section.

DOUT

DIN

SCLK

AIN1

AIN2

GND

0.1µF

10µF

SUPPLY 2.7V

TO 5.25V

SERIAL

INTERFACE

AD7887

0V TO V

INPUT

µC/µP

06191-011

Figure 11. Typical Connection Diagram

Rev. E | Page 11 of 24

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AD7887ARM-REEL7

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