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AD7887ARM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet AD7887
SPECIFICATIONS
V
DD
= 2.7 V to 5.25 V, V
REF
= 2.5 V, external/internal reference unless otherwise noted, f
SCLK
= 2 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter A Version
1
B Version
1
Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio (SNR)
2,
3
71 71 dB typ f
IN
= 10 kHz sine wave, f
SAMPLE
= 125 kSPS
Total Harmonic Distortion (THD)
2
−80 −80 dB typ f
IN
= 10 kHz sine wave, f
SAMPLE
= 125 kSPS
Peak Harmonic or Spurious Noise
2
–80 −80 dB typ f
IN
= 10 kHz sine wave, f
SAMPLE
= 125 kSPS
Intermodulation Distortion (IMD)
2
Second-Order Terms −80 −80 dB typ fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
Third-Order Terms
−80
−80
dB typ
SAMPLE
Channel-to-Channel Isolation
2
−80 −80 dB typ f
IN
= 25 kHz
Full-Power Bandwidth 2.5 2.5 MHz typ @ 3 dB
DC ACCURACY Any channel
Resolution 12 12 Bits
Integral Nonlinearity
2
±2 ±1 LSB max
Differential Nonlinearity
2
±2 ±1 LSB max Guaranteed no missing codes to 11 bits (A Grade)
Offset Error
2
±3 ±3 LSB max V
DD
= 5 V, dual-channel mode
±4 ±4 LSB max V
DD
= 3 V, dual-channel mode
±6 ±6 LSB typ Single-channel mode
Offset Error Match
2
0.5 0.5 LSB max
Gain Error
2
±2 ±2 LSB max Dual-channel mode
±1 ±1 LSB max Single-channel mode, external reference
±6 ±6 LSB typ Single-channel mode, internal reference
Gain Error Match
2
2
2
LSB max
ANALOG INPUT
Input Voltage Ranges 0 to V
REF
0 to V
REF
V
Leakage Current ±5 ±5 μA max
Input Capacitance 20 20 pF typ
REFERENCE INPUT/OUTPUT
REF
IN
Input Voltage Range
2.5/V
DD
2.5/V
DD
V min/max
Input Impedance 10 10 kΩ typ Very high impedance if internal reference disabled
REF
OUT
Output Voltage 2.45/2.55 2.45/2.55 V min/max
REF
OUT
Temperature Coefficient ±50 ±50 ppm/°C typ
LOGIC INPUTS
Input High Voltage, V
INH
2.4 2.4 V min V
DD
= 4.75 V to 5.25 V
2.1 2.1 V min V
DD
= 2.7 V to 3.6 V
Input Low Voltage, V
INL
0.8 0.8 V max V
DD
= 2.7 V to 5.25 V
Input Current, I
IN
±1 ±1 μA max Typically 10 nA, V
IN
= 0 V or V
DD
Input Capacitance, C
IN
4
10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
SOURCE
V
DD
− 0.5 V
DD
− 0.5 V min V
DD
= 2.7 V to 5.25 V
Output Low Voltage, V
OL
0.4 0.4 V max I
SINK
= 200 μA
Floating-State Leakage Current ±1 ±1 μA max
Floating-State Output Capacitance
5
10 10 pF max
Output Coding
Straight (Natural) Binary
Rev. E | Page 3 of 24
AD7887 Data Sheet
Parameter A Version
1
B Version
1
Unit Test Conditions/Comments
CONVERSION RATE
Throughput Time 16 16 SCLK cycles Conversion time plus acquisition time is 125 kSPS,
with 2 MHz Clock
Track/Hold Acquisition Time
2
1.5 1.5 SCLK cycles
Conversion Time 14.5 14.5 SCLK cycles 7.25 μs (2 MHz Clock)
POWER REQUIREMENTS
V
DD
+2.7/+5.25 +2.7/+5.25 V min/max
I
DD
Normal Mode
5
(Mode 2)
Static 700 700 μA max
Operational (f
SAMPLE
= 125 kSPS) 850 850 μA typ Internal reference enabled
700 700 μA typ Internal reference disabled
Using Standby Mode (Mode 4) 450 450 μA typ f
SAMPLE
= 50 kSPS
Using Shutdown Mode (Modes 1, 3) 120 120 μA typ f
SAMPLE
= 10 kSPS
12 12 μA typ f
SAMPLE
= 1 kSPS
Standby Mode
6
210 210 μA max V
DD
= 2.7 V to 5.25 V
Shutdown Mode
6
1 1 μA max V
DD
= 2.7 V to 3.6 V
2 2 μA max V
DD
= 4.75 V to 5.25 V
Normal Mode Power Dissipation 3.5 3.5 mW max V
DD
= 5 V
2.1 2.1 mW max V
DD
= 3 V
Shutdown Power Dissipation 5 5 μW max V
DD
= 5 V
3 3 μW max V
DD
= 3 V
Standby Power Dissipation 1.05 1.05 mW max V
DD
= 5 V
630 630 μW max V
DD
= 3 V
1
Temperature range for A and B versions is −40°C to +125°C.
2
See the Terminology section.
3
SNR calculation includes distortion and noise components.
4
Sample tested at +25°C to ensure compliance.
5
All digital inputs at GND except
CS
at V
DD
. No load on the digital outputs. Analog inputs at GND.
6
SCLK at GND when SCLK off. All digital inputs at GND except for
CS
at V
DD
. No load on the digital outputs. Analog inputs at GND.
Rev. E | Page 4 of 24
Data Sheet AD7887
TIMING SPECIFICATIONS
1
Table 2.
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V
Unit Description
f
SCLK
2
2 2 MHz max
t
CONVERT
14.5 × t
SCLK
14.5 × t
SCLK
t
ACQ
1.5 × t
SCLK
1.5 × t
SCLK
Throughput time = t
CONVERT
+ t
ACQ
= 16 t
SCLK
t
1
10 10 ns min
CS
to SCLK setup time
t
2
3
30 60 ns max Delay from
CS
until DOUT three-state disabled
t
3
3
75 100 ns max Data access time after SCLK falling edge
t
4
20 20 ns min Data setup time prior to SCLK rising edge
t
5
20 20 ns min Data valid to SCLK hold time
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK high pulse width
t
7
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK low pulse width
t
8
4
80 80 ns max
CS
rising edge to DOUT high impedance
t
9
5 5 μs typ Power-up time from shutdown
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA I
OL
200µA I
OH
1.6V
TO
OUTPUT
PIN
C
L
50pF
06191-002
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. E | Page 5 of 24
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AD7887ARM

Mfr. #:
Buy AD7887ARM
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2.7V-5.25V Micropwr 2-Ch 125kSPS 12-Bit
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