LT3582EUD#PBF Datasheet LT3582EUD-5#TRPBF, LT3582EUD-12#TRPBF, LT3582EUD#TRPBF | P10-P12

LT3582/LT3582-5/LT3582-12

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OPERATION

The LT3582 series are dual DC/DC converters, each contain-

ing both a Boost and an Inverting converter. Operation can

be best understood by referring to the Block Diagram. The

Boost and Inverting converters each use a novel control

technique, which simultaneously varies both peak inductor

current and switch off time. This results in high efﬁ ciency

over a large load range and low output voltage ripple. In

addition, this technique further minimizes output ripple

when the switching frequency is in the audio band.

Boost Converter: The Boost converter uses a grounded

source NMOS power transistor as the main switching ele-

ment. The current in the NMOS is constantly monitored and

controlled, along with the off-time of the switch to achieve

regulation of V

OUTP

. The V

OUTP

voltage is divided by the

internal programmable (LT3582 only) resistor divider to

create FBP. The voltage on FBP is compared to an internal

reference and ampliﬁ ed, creating an error signal on the

VCP node which commands the appropriate peak inductor

current and off time for the subsequent switching cycle.

Inverting Converter: The Inverting converter uses a power

PMOS transistor with the source connected to V

. This

topology requires only one external inductor, instead of

the normally required two inductors plus ﬂ ying capacitor.

Regulation is achieved in a similar manner as the Boost.

Output Power-Up Sequencing: After an initial start-up

delay (T

START-UP

= 64s typical), the outputs V

OUTP

and

OUTN

rise (in magnitude) simultaneously with the LT3582-5/

LT3582-12 or in one of four selectable sequences with

the LT3582. Using the I

C interface, the LT3582 outputs

can be conﬁ gured such that (1) they both rise simultane-

ously, (2) V

OUTP

rises to regulation before V

OUTN

rises, (3)

OUTN

rises to regulation before V

OUTP

rises, or (4) neither

output rises. The outputs of the LT3582-5 and LT3582-12

are pre-conﬁ gured to rise simultaneously.

The ramp rates of the outputs are proportional to the ramp

rates of their respective RAMP pins. A capacitor is placed

between each RAMP pin and ground. The RAMP pins are

discharged during shutdown. Once enabled, conﬁ gurable

(LT3582) or pre-conﬁ gured (LT3582-5/LT3582-12) cur-

rents charge each RAMP pin in the desired sequence

causing the outputs to rise.

Output Power-Down Discharge: The power-down dis-

charge feature is permanently enabled on the LT3582-5

and LT3582-12 and can be enabled or disabled through

C on the LT3582. Upon SHDN falling, and when power-

down discharge is enabled, internal transistors will acti-

vate to assist in discharging the outputs toward ground.

When power-down discharge is disabled, the chip powers

down immediately after SHDN falls and the outputs will

discharge on their own depending on their external load

capacitances and currents.

OTP Memory (LT3582 Only): The LT3582 includes 22 bits

of user programmable output settings and 1 programming

lockout bit. Parameters such as positive and negative output

voltages and power sequencing settings can be changed

in real time with the integrated I

C interface. Settings can

then be made permanent by programming to the on-chip

non-volatile OTP (One Time Programmable) memory.

LT3582/LT3582-5/LT3582-12

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APPLICATIONS INFORMATION

Figure 1. Data Transfer Over I

C Bus

C Interface

The LT3582 series contains an I

C compatible interface

allowing it to be digitally conﬁ gured. The use of this interface

is optional for the LT3582-5 and LT3582-12 as these parts

are pre-conﬁ gured at the factory. The CA, SDA and SCL

pins can be grounded if the I

C interface is unused.

The I

C interface has reduced input threshold voltages to

allow for direct communication with low voltage digital

ICs (see Electrical Characteristics). I

C communication

is disabled when SHDN is low. After SHDN rises, I

communication is re-enabled after a delay of 64s (typical).

The chip is a read-write slave device which allows the user

to read the current settings and, for the LT3582, write

new ones. Most settings can be made permanent via the

One-Time-Programmable memory. The chip will always

enable using the data stored in OTP and the LT3582 can

be reconﬁ gured after power-up.

START and STOP Conditions

When the bus is idle, both SCL and SDA are high. A bus

master signals the beginning of a transmission with a START

condition by transitioning SDA from high to low while SCL

is high, as shown in Figure 1. When the master has ﬁ nished

communicating with the slave, it issues a STOP condition

by transitioning SDA from low to high while SCL is high.

The bus is then free for another transmission.

ACKnowledge

The acknowledge signal (ACK) is used in handshaking

between transmitter and receiver to indicate that the most

recent byte of data was received. The transmitter always

releases the SDA line during the acknowledge clock pulse.

When the slave is the receiver, it pulls down the SDA line

so that it remains LOW during this pulse to acknowledge

receipt of the data. If the slave fails to acknowledge

by leaving SDA high, then the master may abort the

transmission by generating a STOP condition. When the

master is receiving data from the slave, the master pulls

down the SDA line during the clock pulse to indicate receipt

of the data. After the last byte has been received the master

leaves the SDA line HIGH (not acknowledge) and issues a

stop condition to terminate the transmission.

Device Addressing

The LT3582 series supports two 7-bit chip addresses

depending on the logic state of the CA pin. The addresses

are 0110 001 (CA = 1) and 1000 101 (CA = 0). Also, there

are seven internal data byte locations as shown in Table 1.

OTP0-OTP2 are the OTP memory bytes. REG0-REG2

are the corresponding volatile registers used for storing

alternate settings. Finally, the Command Register (CMDR)

is used for additional control of the chip.

3582512 F01

SCL

SDA

R/WCHIP

ADDRESS

START

CONDITION

STOP

CONDITION

ACK DATA ACK DATA

1-7

B7 - B0B7 - B0A6 - A0

891-7 8 91-7 8

S P

ACK

LT3582/LT3582-5/LT3582-12

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All data bytes can be read from their assigned register

addresses. Since they share the same register addresses,

reads of the OTP and REG data bytes are differentiated

by their corresponding RSEL (Register Select) bits in the

CMDR register. All data written to register addresses 0-2 is

stored in REGO-REG2. Regardless of the RSEL bits, OTP

bytes cannot be written directly. See the OTP Programming

section for more information.

Data Transfer Protocol

The LT3582 series supports 8-bit data transfers in the

transaction formats shown in Figures 2 and 3. Multiple

data bytes can only be transferred by issuing multiple

transactions.

Figure 2 shows the required format for writing a byte of

data to the LT3582 series. Again, the chip address depends

on the CA pin logic state.

S CHIP ADDR W A REG ADDR A DATA A P

0110 001 OR

1000 101

0 0 00000b2:b0 0 b7:b0 0

FROM MASTER TO SLAVE A: ACKNOWLEDGE (LOW)

FROM SLAVE TO MASTER A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

W WRITE BIT (LOW)

S: START CONDITION

P: STOP CONDITION

Figure 2. I

C Byte Write Transaction

A byte of data is read from the LT3582 series using the

format shown in Figure 3. This transaction requires four I

bytes to read one byte of chip data and must be repeated

for each subsequent byte of data that is read.

S CHIP ADDR W A REG ADDR A

0110 001 OR

1000 101

0 0 00000b2:b0 0

LT3582 Chip Conﬁ guration

Settings such as output voltages and sequencing are

digitally programmable. The chip uses settings from either

the REG or OTP bytes, depending on the states of the

corresponding RSEL bits (0 for OTP and 1 for REG).

During shutdown the RSEL bits are reset low. As a result,

the initial conﬁ guration comes from the OTP data bytes.

After power-up, the conﬁ guration can be changed by writing

new settings to the appropriate REG data byte(s) then

setting the corresponding RSEL bit(s).

Finally, data in the REG bytes can be permanently

programmed to OTP by applying voltage to the V

and setting the WOTP bit in the Command Register. See

the

OTP Programming

section for more information.

LT3582-5/LT3582-12 Chip Conﬁ guration

The LT3582-5/LT3582-12 are shipped from the factory with

the OTP memory pre-programmed and LOCKed which

prohibits subsequent changes to the conﬁ guration. The

conﬁ guration can still be read through the I

C bus and

the RST and SWOFF bits of the CMDR register (described

later) are functional. The following sections describe the

various conﬁ gurable features of the LT3582. The LT3582-5

and LT3582-12 are pre-conﬁ gured as follows: V

and V

are programmed for ±5V or ±12V respectively, LOCK = 1,

IRMP = 00, PDDIS = 1, PUSEQ = 11 and V

PLUS

may be 1

or 0. Since LOCK = 1, subsequent conﬁ guration changes

are prohibited. See

Conﬁ guration Lockout (LOCK Bit)

for

more information.

Registers and OTP

The registers and OTP bytes for the LT3582 series are

organized as shown in Table 1. The CMDR is reset to 00h

upon power-up, during shutdown and during undervoltage

and thermal lockouts.

REG0-REG2 are never reset and must

always be loaded with valid data before use.

The LT3582’s

OTP memory is shipped with all 0’s, and as a result, the

PUSEQ bits are conﬁ gured to disable the outputs. The

PUSEQ bits must be reconﬁ gured to enable the outputs.

APPLICATIONS INFORMATION

S CHIP ADDR R A DATA A P

0110 001 OR

1000 101

1 0 b7:b0 1

Figure 3. I

C Byte Read Transaction

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

LT3582EUD#PBF

Mfr. #:

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Manufacturer:

Analog Devices / Linear Technology

Description:

Switching Voltage Regulators Programmable Boost and Single Inductor Inverting DC/DC Converters with OTP

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