ICS554-01A
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT PECL BUFFER
IDT™ / ICS™
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT 3
ICS554-01A REV C 092309
External Components
The ICS554-01A requires a decoupling capacitor of 0.01µF to be connected between VDD on pin 2 and GND on
pin 7, as well as between VDD on pin 15 and GND on pin 10. These decoupling capacitors should be placed as
close to the device as possible.
To achieve the low output skews that the ICS554-01A is capable of, careful attention must be paid to board layout.
Essentially, all 8 outputs must have identical terminations, loads, and trace geometries. If they do not, the output
skew will be degraded. For example, using a 30Ω series termination on one output (with 33Ω on the others) will
cause at least 15ps of skew.
Termination for PECL or LVPECL Outputs
The clock layout topology shown below is a typical termination for PECL or LVPECL outputs. The two different
layouts mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate PECL/LVPECL compatible outputs.
Therefore, termination resistors (DC current path to ground) or current sources must be used for functionality.
These outputs are designed to drive 50 ohm transmission lines. Matched impedance techniques should be used to
maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. The
figures below show two different layouts which are recommended only as guidelines. Other suitable clock layouts
may exist, but it is recommended that board designers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
PECL or LVPECL Output Termination
LVPECL Output Termination
Z
0
= 50 ohms
F
OUT
F
IN
Z
0
= 50 ohms
50 ohms 50 ohms
C1 RTT
RTT = Z
0
(V
OH
+
V
OL
/
V
CC
-2) -2
1
C1 = 0.1µF to 0.01µF
Z
0
= 50 ohms
F
OUT
F
IN
Z
0
= 50 ohms
Z
0
3.3 V
5
2
3
2
5
2
Z
0
Z
0
3
2
Z
0
