NE570
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6
CIRCUIT DETAILS−RECTIFIER
Figure 8 shows the concept behind the full−wave
averaging rectifier. The input current to the summing node
of the op amp, V
IN
/R
1
, is supplied by the output of the op
amp. If we can mirror the op amp output current into a
unipolar current, we will have an ideal rectifier. The output
current is averaged by R
5
, C
R
, which set the averaging time
constant, and then mirrored with a gain of 2 to become I
G
,
the gain control current.
Figure 9 shows the rectifier circuit in more detail. The op
amp is a one−stage op amp, biased so that only one output
device is on at a time. The non−inverting input, (the base of
Q
1
), which is shown grounded, is actually tied to the internal
1.8 V V
REF
. The inverting input is tied to the op amp output,
(the emitters of Q
5
and Q
6
), and the input summing resistor
R1. The single diode between the bases of Q
5
and Q
6
assures
that only one device is on at a time. To detect the output
current of the op amp, we simply use the collector currents of
the output devices Q
5
and Q
6
. Q
6
will conduct when the
input swings positive and Q
5
conducts when the input
swings negative. The collector currents will be in error by the
α of Q
5
or Q
6
on negative or positive signal swings,
respectively. ICs such as this have typical NPN β’s of 200
and PNP β’s of 40. The α’s of 0.995 and 0.975 will produce
errors of 0.5% on negative swings and 2.5% on positive
swings. The 1.5% average of these errors yields a mere
0.13 dB gain error.
At very low input signal levels the bias current of Q
2
,
(typically 50 nA), will become significant as it must be
supplied by Q
5
. Another low level error can be caused by DC
coupling into the rectifier. If an offset voltage exists between
the V
IN
input pin and the base of Q
2
, an error current of
V
OS
/R
1
will be generated. A mere 1.0 mV of offset will
cause an input current of 100 nA, which will produce twice
the error of the input bias current. For highest accuracy, the
rectifier should be coupled capacitively. At high input levels
the β of the PNP Q
6
will begin to suffer, and there will be an
increasing error until the circuit saturates. Saturation can be
avoided by limiting the current into the rectifier input to
250 mA. If necessary, an external resistor may be placed in
series with R
1
to limit the current to this value. Figure 10
shows the rectifier accuracy versus input level at a frequency
of 1.0 kHz.
−
+
R
1
V
IN
I = V
IN
/R
1
V+
I
G
R
5
10 kW
C
R
Figure 8. Rectifier Concept
R
5
10 kW
C
R
Q
8
Q
9
R
1
10 kW
V
IN
Q
5
Q
6
Q
7
Q
4
V+
V−
Q
2
Q
1
I
1
I
2
Q
3
NOTE:
I
G
= 2
D
1
V
IN
avg
R
1
Figure 9. Simplified Rectifier Schematic
ERROR GAIN dB
+1
0
−1
−40 −20 0
RECTIFIER INPUT dBm
Figure 10. Rectifier Accuracy
