NE570
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7
At very high frequencies, the response of the rectifier will
fall off. The roll−off will be more pronounced at lower input
levels due to the increasing amount of gain required to switch
between Q
5
or Q
6
conducting. The rectifier frequency
response for input levels of 0 dBm, −20 dBm, and −40 dBm
is shown in Figure 11. The response at all three levels is flat
to well above the audio range.
0
3
10 k 1 MEG
INPUT = 0 dBm
−20 dBm
−40 dBm
FREQUENCY (Hz)
GAIN ERROR (dB)
Figure 11. Rectifier Frequency Response
vs. Input Level
VARIABLE GAIN CELL
Figure 12 is a diagram of the variable gain cell. This is a
linearized two−quadrant transconductance multiplier. Q
1
,
Q
2
and the op amp provide a predistorted drive signal for the
gain control pair, Q
3
and Q
4
. The gain is controlled by I
G
and
a current mirror provides the output current.
V+
V−
Q
2
Q
1
NOTE:
I
OUT
=
I
G
I
1
R
2
20 kW
V
IN
I
IN
I
2
( = 2 I
1
)
280 mA
−
+
I
1
140 mA
Q
4
Q
3
I
G
I
IN
=
V
IN
R
2
I
G
I
1
Figure 12. Simplified DG Cell Schematic
The op amp maintains the base and collector of Q
1
at
ground potential (V
REF
) by controlling the base of Q
2
. The
input current I
IN
(= V
IN
/R
2
) is thus forced to flow through
Q
1
along with the current I
1
, so I
C1
= I
1
+ I
IN
. Since I
2
has
been set at twice the value of I
1
, the current through Q
2
is:
I
2
* (I
1
) I
IN)
+ I
1
* I
IN
+ I
C2.
The op amp has thus forced a linear current swing between
Q
1
and Q
2
by providing the proper drive to the base of Q
2
.
This drive signal will be linear for small signals, but very
non−linear for large signals, since it is compensating for the
non−linearity of the differential pair, Q
1
and Q
2
, under large
signal conditions.
The key to the circuit is that this same predistorted drive
signal is applied to the gain control pair, Q
3
and Q
4
. When
two differential pairs of transistors have the same signal
applied, their collector current ratios will be identical
regardless of the magnitude of the currents. This gives us:
I
C1
I
C2
+
I
C4
I
C3
+
I
1
) I
IN
I
1
* I
IN
plus the relationships I
G
= I
C3
+ I
C4
and I
OUT
= I
C4
− I
C3
will yield the multiplier transfer function,
I
OUT
+
I
G
I
1
I
IN
+
V
IN
R
2
I
G
I
1
This equation is linear and temperature−insensitive, but it
assumes ideal transistors.
4
3
2
1
0.34
−6 0 +6
4 mV
3 mV
2 mv
1 mV
INPUT LEVEL (dBm)
% THD
V
OS
= 5 mV
Figure 13. DG Cell Distortion vs. Offset Voltage
If the transistors are not perfectly matched, a parabolic,
non−linearity is generated, which results in second
harmonic distortion. Figure 13 gives an indication of the
magnitude of the distortion caused by a given input level and
offset voltage. The distortion is linearly proportional to the
magnitude of the offset and the input level. Saturation of the
gain cell occurs at a +8.0 dBm level. At a nominal operating
level of 0 dBm, a 1.0 mV offset will yield 0.34% of second
harmonic distortion. Most circuits are somewhat better than
