Table 10: DDR2 I
DD
Specifications and Conditions – 1GB (Die Revisions E and G) (Continued)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
Parameter Symbol -800 -667 Units
Operating burst read current: All device banks open; Continuous burst read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
I
DD4R
1
1308 908 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
I
DD5
2
2240 2160 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
I
DD6
2
56 56 mA
Operating bank interleave read current: All device banks interleaving reads; I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK (I
DD
),
t
RC =
t
RC
(I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
I
DD7
1
1788 1428 mA
Notes:
1. Value calculated as one module rank in this operating condition; all other module ranks
in I
DD2P
(CKE LOW) mode.
2. Value calculated reflects all module ranks in this operating condition.
Table 11: DDR2 I
DD
Specifications and Conditions – 1GB (Die Revision H)
Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-
ponent data sheet
Parameter Symbol -800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
DD0
1
348 328 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL = CL
(I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
DD4W
I
DD1
1
408 388 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is LOW;
Other control and address bus inputs are stable; Data bus inputs are floating
I
DD2P
2
56 56 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
I
DD2Q
2
208 208 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH, S# is
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
I
DD2N
2
240 208 mA
Active power-down current: All device banks open;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
2
160 120 mA
Slow PDN exit
MR[12] = 1
80 80
512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
I
DD
Specifications
PDF: 09005aef831ec770
htf8c64_128x64hdz.pdf - Rev. E 4/14 EN
12
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© 2008 Micron Technology, Inc. All rights reserved.
