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MF0MOU2101DA4,118

P1-P3P4-P6P7-P9P10-P12P13-P15
MF0ICU2_SDS_32 © NXP B.V. 2009. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3 — 19 May 2009
171432 4 of 15
NXP Semiconductors
MF0ICU2
MIFARE Ultralight C
6. Block diagram
7. Functional description
7.1 Block description
The MF0ICU2 chip consists of the 1536-bit EEPROM, the RF-Interface and the Digital
Control Unit. Energy and data are transferred via an antenna, which consists of a coil with
a few turns directly connected to the MF0ICU2. No further external components are
necessary. (For details on antenna design please refer to the document Ref. 6 “MIFARE
(Card) Coil Design Guide”.)
• RF-Interface:
– Modulator/Demodulator
– Rectifier
– Clock Regenerator
– Power On Reset
– Voltage Regulator
• Crypto coprocessor: Triple Data Encryption Standard (3DES) coprocessor
• Crypto control unit: controls Crypto coprocessor operations
• Command Interpreter: Handles the commands supported by the MF0ICU2 in order to
access the memory
• EEPROM-Interface
• EEPROM: The 1536 bits are organized in 48 pages with 32 bits each. 80 bits are
reserved for manufacturer data. 32 bits are used for the read-only locking mechanism.
32 bits are available as an OTP area. 1152 bits are user programmable read/write
memory.
Fig 2. Block diagram
001aah999
antenna
RF-INTERFACE
DIGITAL CONTROL UNIT
EEPROM
CRYPTO
CO PROCESSOR
CRYPTO
CONTROL UNIT
COMMAND
INTERPRETER
EEPROM
INTERFACE
MF0ICU2_SDS_32 © NXP B.V. 2009. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3 — 19 May 2009
171432 5 of 15
NXP Semiconductors
MF0ICU2
MIFARE Ultralight C
7.2 State diagram and logical states description
The commands are initiated by the PCD and controlled by the Command Interpreter of the
MF0ICU2. It handles the internal states (as shown in Figure 3 “State diagram”) and
generates the appropriate response.
For a correct implementation of an anticollision procedure please refer to the documents
in Section 10 “References”.
Remark: Not shown in this diagram: In each state the command interpreter returns to the Idle state
if an unexpected command is received. If the IC has already been in the Halt state before it returns
to the Halt state in such a case.
Fig 3. State diagram
001aai000
AUTHENTICATED
ACTIVE
READY 1
HALTIDLE
POR
SELECT
of cascade level 1
READ
from address 0
READ
from address 0
WRITE
of 4 byte
WRITE
of 4 byte
READ
of 16 byte
READ
of 16 byte
ANTICOLLISION
ANTICOLLISION
AUTHENTICATE
REQA
WUPA
WUPA
HALT
HALT
SELECT
of cascade level 2
READY 2
identification
and
selection
procedure
memory
operations
MF0ICU2_SDS_32 © NXP B.V. 2009. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3 — 19 May 2009
171432 6 of 15
NXP Semiconductors
MF0ICU2
MIFARE Ultralight C
7.3 Memory organization
The 1536-bit EEPROM memory is organized in 48 pages with 32 bits each. In the erased
state the EEPROM cells are read as a logical “0”, in the written state as a logical “1”.
7.3.1 UID/serial number
The unique 7 byte serial number (UID) and its two Block Check Character Bytes (BCC)
are programmed into the first 9 bytes of the memory. It therefore covers page 00h, page
01h and the first byte of page 02h. Due to security and system requirements these bytes
are write-protected after having been programmed by the IC manufacturer after
production.
According to ISO/IEC14443-3 BCC0 is defined as CT ⊕ SN0 ⊕ SN1 ⊕ SN2.
Abbreviations CT stays for Cascade Tag byte (88h) and BCC1 is defined as SN3 ⊕ SN4
⊕ SN5 ⊕ SN6.
SN0 holds the Manufacturer ID for NXP (04h) according to ISO/IEC14443-3 and
ISO/IEC 7816-6 AMD.1.
Table 3. Memory organization
Page address Byte number
Decimal Hex 0 1 2 3
0 00h serial number
1 01h serial number
2 02h serial number internal lock bytes lock bytes
3 03h OTP OTP OTP OTP
4 to 39 04h to 27h user memory user memory user memory user memory
40 28h lock bytes lock bytes - -
41 29h 16-bit counter 16-bit counter - -
42 2Ah authentication configuration
43 2Bh authentication configuration
44 to 47 2Ch to 2Fh authentication key
Fig 4. UID/serial number
001aai001
MSBit LSBit
page 0
byte
check byte 0
serial number
part 1
serial number
part 2
manufacturer ID for NXP (04h)00000100
0123
page 1
0123
page 2
0123
internal
check byte 1
lock bytes
P1-P3P4-P6P7-P9P10-P12P13-P15

MF0MOU2101DA4,118

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Manufacturer:
NXP Semiconductors
Description:
RF Transceiver MIFARE Ultralight C PLLMC
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