LTC1471CS#PBF

4
LTC1470/LTC1471
14701fa
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
PIN FUNCTIONS
UUU
LTC1470
OUT (Pins 1, 8): Output Pins. The outputs of the LTC1470
are switched between three operating states: OFF, 3.3V
and 5V. These pins are protected against accidental short
circuits to ground by SafeSlot current limit circuitry which
protects the socket, the card, and the system power
supplies against damage. A second level of protection is
provided by thermal shutdown circuitry which protects
both switches against over-temperature conditions.
5V
IN
(Pin 2): 5V
Input Supply Pin. The 5V
IN
supply pin
serves two purposes. The first purpose is as the power
supply input for the 5V NMOS switch. The second purpose
is to provide power for the input, gate drive, and protection
circuitry for both the 3.3V and 5V V
CC
switches. This pin
must therefore be continuously powered.
EN1, EN0 (Pins 3, 4): Enable Inputs. The two V
CC
Enable
inputs are designed to interface directly with industry
standard PCMCIA controllers and are high impedance
CMOS gates with ESD protection diodes to ground, and
should not be forced above 5V
IN
or below ground. Both
inputs have about 100mV of built-in hysteresis to ensure
clean switching between operating modes. The LTC1470
is designed to operate
without
12V power. The gates of the
V
CC
NMOS switches are powered by charge pumps from
the 5V
IN
supply pins (see Applications Information section
for more detail). The Enable inputs should be turned off
(both asserted high or both asserted low) at least 100µs
before the 5V
IN
power is removed to ensure that both V
CC
NMOS switch gates are fully discharged and both switches
are in the high impedance mode.
GND (Pin 5): Ground Connection.
3V
IN
(Pins 6, 7): 3V
Input Supply Pins. The 3V
IN
supply
pins serve as the power supply input for the 3.3V switches.
These pins do not provide any power to the internal control
circuitry and therefore do not consume any power when
unloaded or turned off.
JUNCTION TEMPERATURE (°C)
0
0
5V SWITCH RESISTANCE ()
0.05
0.10
0.15
0.20
0.25
0.30
25 50 75 100
1470/71 G06
125
PROGRAMMED
TO 5V
5V Switch Resistance
TIME (ms)
0.2
INRUSH CURRENT (A)OUTPUT VOLTAGE (V)
0
1
1.4
1470/71 G08
6
4
0
0.2
0.6
1.0
2
3
2
0
0.4
0.8
1.2
C
OUT
= 15µF
R
OUT
= 10
T
J
= 25°C
CURRENT
LIMITED
C
OUT
= 150µF
R
OUT
= 10
Inrush Current (5V Switch)Inrush Current (3.3V Switch)
TIME (ms)
–0.2
INRUSH CURRENT (A)OUTPUT VOLTAGE (V)
0
1
1.4
1470/71 G09
6
4
0
0.2
0.6
1.0
2
3
2
0
0.4
0.8
1.2
T
J
= 25°C
C
OUT
= 15µF
R
OUT
= 6.6
C
OUT
= 150µF
R
OUT
= 6.6
C
OUT
= 150µF
R
OUT
= 6.6
(LTC1470 or 1/2 LTC1471)
5
LTC1470/LTC1471
14701fa
PIN FUNCTIONS
UUU
TTL-TO-CMOS
CONVERTER
OSCILLATOR
AND BIAS
GATE CHARGE
AND
DISCHARGE
CONTROL LOGIC
CHARGE
PUMP
GATE CHARGE
AND
DISCHARGE
CONTROL LOGIC
CURRENT LIMIT
AND THERMAL
SHUTDOWN
5V
IN
0.14
0.12
OUTPUT
3V
IN
BREAK-BEFORE-
MAKE SWITCH
AND CONTROL
TTL-TO-CMOS
CONVERTER
EN0
EN1
LTC1470-BD01
BLOCK DIAGRAM
W
LTC1471
AOUT, BOUT(Pins 1, 16, 8, 9): Output Pins. The outputs
of the LTC1471 are switched between three operating
states: OFF, 3.3V and 5V. These pins are protected against
accidental short circuits to ground by SafeSlot current
limit circuitry which protects the socket, the card, and the
system power supplies against damage. A second level of
protection is provided by thermal shutdown circuitry.
5V
IN
(Pins 2, 10): 5V
Input Supply Pins. The 5V
IN
supply
pins serve two purposes. The first purpose is as the power
supply input for the 5V NMOS switches. The second
purpose is to provide power for the input, gate drive, and
protection circuitry. These pins must therefore be con-
tinuously powered.
EN1, EN0 (Pins 3, 4, 11, 12): Enable Inputs. The enable
inputs are designed to interface directly with industry
standard PCMCIA controllers and are high impedance
CMOS gates with ESD protection diodes to ground, and
should not be forced above 5V
IN
or below ground. All four
inputs have about 100mV of built-in hysteresis to ensure
clean switching between operating modes. The LTC1471
is designed to operate
without
12V power. The gates of the
V
CC
NMOS switches are powered by charge pumps from
the 5V
IN
supply pins (see Applications Information section
for more detail). The enable inputs should be turned off at
least 100µs before the 5V
IN
power is removed to ensure
that all NMOS switch gates are fully discharged and are in
the high impedance mode.
GND (Pins 5, 13): Ground Connections.
3V
IN
(Pins 6, 7, 14, 15): 3V
Input Supply Pins. The 3V
IN
supply pins serve as the power supply input for the 3.3V
switches. These pins do not not provide any power to the
internal control circuitry, and therefore, do not consume
any power when unloaded or turned off.
(LTC1470 or 1/2 LTC1471)
6
LTC1470/LTC1471
14701fa
OPERATION
U
The LTC1470 (or 1/2 of the LTC1471) consists of the
following functional blocks:
Input TTL/CMOS Converters
The enable inputs are designed to accommodate a wide
range of 3V and 5V logic families. The input threshold
voltage is approximately 1.4V with approximately 100mV
of hysteresis. The inputs enable the bias generator, the
gate charge pumps and the protection circuity which are
powered from the 5V supply. Therefore, when the inputs
are turned off, the entire circuit is powered down and the
5V
supply current drops below 1µA.
XOR Input Circuitry
By employing an XOR function, which locks out the 3.3V
switch when the 5V switch is turned on and locks out the
5V switch when the 3.3V switch is turned on, there is no
danger of both switches being on at the same time. This
XOR function also makes it possible to work with either
active -low or active-high PCMCIA V
CC
switch control logic
(see Applications Information section for further details).
Break-Before-Make Switch Control
Built-in delays are provided to ensure that the 3.3V and 5V
switches are non-overlapping. Further, the gate charge
pump includes circuitry which ramps the NMOS switches
on slowly (400µs typical rise time) but turns them off
much more quickly (typically 10µs).
Bias, Oscillator and Gate Charge Pump
When either the 3.3V or 5V switch is enabled, a bias
current generator and high frequency oscillator are turned
on. The on-chip capacitive charge pump generates ap-
proximately 12V of gate drive for the internal low R
DS(ON)
NMOS V
CC
switches from the 5V
IN
power supply. There-
fore, an external 12V supply is not required to switch the
V
CC
output. The 5V
IN
supply current drops below 1µA
when both switches are turned off.
Gate Charge and Discharge Control
All switches are designed to ramp on slowly (400µs typical
rise time). Turn-off time is much quicker (typically 10µs).
To ensure that both V
CC
NMOS switch gates are fully
discharged, program the switch to the high impedance
mode at least 100µs before turning off the 5V power
supply.
Switch Protection
Both switches are protected against accidental short cir-
cuits with SafeSlot foldback current limit circuits which
limit the output current to typically 1A when the output is
shorted to ground. Both switches also have thermal shut-
down which limits the power dissipation to safe levels.
APPLICATIONS INFORMATION
WUU
U
Figure 1. Direct Interface to CL-PD6710 PCMCIA Controller
LTC1470
EN0
EN1
3V
IN
5V
IN
3V
IN
OUT
OUT
GND
+
3.3V
5V
0.1µF
0.1µF
1µF
TANT
10k
(OFF/3.3V/5V)
TO CARD
V
CC
PINS
CL-PD6710
V
CC
_5
V
CC
_3
1470/71 F01
The LTC1470/LTC1471 are designed to interface directly
with industry standard PCMCIA card controllers.
Interfacing with the CL-PD6710
Figure 1 is a schematic diagram showing the LTC1470
interfaced with a standard PCMCIA slot controller. The
LTC1470 accepts logic control directly from the CL-PD6710.
The XOR input function allows the LTC1470 to interface
directly to the active-low V
CC
control outputs of the CL-
PD6710 for 3.3V/5V voltage selection (see the following
Switch Truth Table). Therefore, no “glue” logic is required
to interface to this PCMCIA compatible card controller.

LTC1471CS#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switch ICs - Various Dual PCMCIA Protected Vcc Switch
Lifecycle:
New from this manufacturer.
Delivery:
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