MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
_______________________________________________________________________________________ 7
TWO-TONE IMD PLOT (32,768-POINT
DATA RECORD, COHERENT SAMPLING)
MAX1419 toc19
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
252015105
-100
-80
-60
-40
-20
0
-120
030
f
CLK
= 65.0117MHz
f
IN1
= 10.0010MHz
f
IN2
= 15.0010MHz
A
IN1
= A
IN2
= -7dBFS
2f
IN1
- f
IN2
2f
IN2
- f
IN1
f
IN1
f
IN2
SFDR1/SFDR2 vs. TEMPERATURE
(f
CLK
= 65.0117MHz,
f
IN
= 15.0010MHz, A
IN
= -1dBFS)
MAX1419 toc15
TEMPERATURE (°C)
SFDR1/SFDR2 (dBc)
603510-15
84
88
92
96
100
80
-40 85
SFDR2
SFDR1
HD2/HD3 vs. TEMPERATURE
(f
CLK
= 65.0117MHz,
f
IN
= 15.0010MHz, A
IN
= -1dBFS)
MAX1419 toc16
TEMPERATURE (°C)
HD2/HD3 (dBc)
603510-15
-100
-95
-90
-85
-105
-40 85
HD3
HD2
POWER DISSIPATION vs. TEMPERATURE
(f
CLK
= 65.0117MHz,
f
IN
= 15.0010MHz, A
IN
= -1dBFS)
MAX1419 toc17
TEMPERATURE (°C)
POWER DISSIPATION (mW)
603510-15
1971
1972
1973
1974
1975
1976
1970
-40 85
POWER DISSIPATION vs. SUPPLY VOLTAGE
(f
CLK
= 65.0117MHz,
f
IN
= 15.0010MHz, A
IN
= -1dBFS)
MAX1419 toc18
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
5.205.154.90 4.95 5.00 5.05 5.10
1850
1900
1950
2000
2050
2100
2150
2200
1800
4.85 5.25
Typical Operating Characteristics (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 65MHz, T
A
= +25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 2, 3, 6, 9, 12, 14–17,
20, 23, 26, 27, 30, 52–56, EP
GND
Converter Ground. Analog, digital, and output driver grounds are internally
connected to the same potential. Connect the converter’s EP to GND.
4 CLKP Differential Clock, Positive Input Terminal
5 CLKN Differential Clock, Negative Input Terminal
7, 8, 18, 19, 21, 22, 24, 25, 28
AV
CC
Analog Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF
capacitors.
10 INP Differential Analog Input, Positive Terminal
11 INN Differential Analog Input, Negative/Complementary Terminal
13 CM Common-Mode Reference Terminal
29 DV
CC
Digital Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF
capacitors.
31, 41, 42, 51 DRV
CC
Digital Output Driver Supply Voltage. Provide local bypassing to ground with
0.1µF to 0.22µF capacitors.
32 DOR
Data Overrange Bit. This control line flags an overrange condition in the ADC.
If DOR transitions high, an overrange condition was detected. If DOR remains low,
the ADC operates within the allowable full-scale range.
33 D0 Digital CMOS Output Bit 0 (LSB)
34 D1 Digital CMOS Output Bit 1
35 D2 Digital CMOS Output Bit 2
36 D3 Digital CMOS Output Bit 3
37 D4 Digital CMOS Output Bit 4
38 D5 Digital CMOS Output Bit 5
39 D6 Digital CMOS Output Bit 6
40 D7 Digital CMOS Output Bit 7
43 D8 Digital CMOS Output Bit 8
44 D9 Digital CMOS Output Bit 9
45 D10 Digital CMOS Output Bit 10
46 D11 Digital CMOS Output Bit 11
47 D12 Digital CMOS Output Bit 12
48 D13 Digital CMOS Output Bit 13
49 D14 Digital CMOS Output Bit 14 (MSB)
50 DAV
Data Valid Output. This output can be used as a clock control line to drive an
external buffer or data-acquisition system. The typical delay time between the
falling edge of the converter clock and the rising edge of DAV is 6.5ns.
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
_______________________________________________________________________________________ 9
Detailed Description
Figure 1 provides an overview of the MAX1419 archi-
tecture. The MAX1419 employs an input T/H amplifier,
which has been optimized for low thermal noise and
low distortion. The high-impedance differential inputs to
the T/H amplifier (INP and INN) are self-biased at
3.38V, and support a full-scale differential input voltage
of 2.56V
P-P
. The output of the T/H amplifier is fed to a
multistage pipelined ADC core, which has also been
optimized to achieve a very low thermal noise floor and
low distortion.
A clock buffer receives a differential input clock wave-
form and generates a low-jitter clock signal for the input
T/H. The signal at the analog inputs is sampled at the
rising edge of the differential clock waveform. The dif-
ferential clock inputs (CLKP and CLKN) are high-
impedance inputs, are self-biased at 2.4V, and support
differential clock waveforms from 0.5V
P-P
to 3.0V
P-P
.
The outputs from the multistage pipelined ADC core
are delivered to error correction and formatting logic-
which in turn, deliver the 15-bit output code in two’s-
complement format to digital output drivers. The output
drivers provide CMOS-compatible outputs with levels
programmable over a 2.3V to 3.5V range.
Analog Inputs and
Common Mode (INP, INN, CM)
The signal inputs to the MAX1419 (INP and INN) are
balanced differential inputs. This differential configura-
tion provides immunity to common-mode noise coupling
and rejection of even-order harmonic terms. The differ-
ential signal inputs to the MAX1419 should be AC-cou-
pled and carefully balanced in order to achieve the best
dynamic performance (see the Applications Information
section for more detail). AC-coupling of the input signal
is easily accomplished because the MAX1419 inputs
are self-biasing as illustrated in Figure 2. Although the
T/H inputs are high impedance, the actual differential
input impedance is nominally 1kΩ because of the two
500Ω bias resistors connected from each input to the
common-mode reference.
The CM pin provides a monitor of the input common-
mode self-bias potential. In most applications, in which
the input signal is AC-coupled, this pin is not connect-
ed. If DC-coupling of the input signal is required, this
pin may be used to construct a DC servo loop to con-
trol the input common-mode potential. See the
Applications Information section for more details.
T/H
CORRECTION
LOGIC + OUTPUT
BUFFERS
INTERNAL
TIMING
INTERNAL
REFERENCE
INP
INN
CM
CLKP
CLKN
DAV
15
DATA BITS D0 THROUGH D14
AV
CC
DRV
CC
DV
CC
GND
MULTISTAGE
PIPELINE ADC CORE
CLOCK
BUFFER
MAX1419
Figure 1. Simplified MAX1419 Block Diagram
BUFFER
INTERNAL REFERENCE
AND BIASING CIRCUIT
T/H AMPLIFIER
T/H AMPLIFIER
500Ω
500Ω
CM
INP
INN
TO 1. QUANTIZER STAGE
TO 1. QUANTIZER STAGE
1kΩ
Figure 2. Simplified Analog and Common-Mode Input Architecture

MAX1419ETN+TD

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC
Lifecycle:
New from this manufacturer.
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