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ADCLK946/PCBZ

P1-P3P4-P6P7-P8
UG-069 Evaluation Board User Guide
Rev. 0 | Page 4 of 8
CLOCK OUTPUTS
The ADCLK946 has six differential outputs. All differential
clock outputs on the evaluation board are biased to GND via
200 Ω and ac-coupled to the SMAs. From the SMAs, use
matched 50 Ω coaxial cables into the oscilloscope for
evaluation. See the evaluation board schematic in Figure 4 for
more details.
Table 2. Power Connections via P1
Label ADCLK946
GND Connect to GND
VCC Connect to 3.3 V
VEE Connect to GND
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
LVPECL
CLK
V
T
V
REF
CLK
ADCLK946
REFERENCE
08668-001
Figure 3. ADCLK946 1:6 Clock/Data Buffer Block Diagram
Evaluation Board User Guide UG-069
Rev. 0 | Page 5 of 8
EVALUATION BOARD SCHEMATIC AND ARTWORK
50 OHMS
50 OHMS
50 OHMS
50 OHMS
50 OHMS => SINGLE ENDED
50 OHMS
VT
VEE
CLK
VREF
VEE
50 OHMS
50 OHMS
Q5B
VEE Q5
Q4B
Q4VEE
VCC
Q3B
VCC Q1
Q1B
VEE
Q3
VCC
50 OHMS
50 OHMS
50 OHMS
50 OHMS
50 OHMS
BYPASS CAPACITORS (DUT)
SAME AS ADCLK954 ENGR BRD
ORDER WEILAND 25.600.5453.0 PLUG
Q0B
Q2
Q2B
50 OHMS
CLKB
Q0
LABEL "VCC (3.3V)"
LABEL "VEE (GND)"
BYPASS CAPACITORS (SUPPLY)
STITCHING RESISTORS (O OHM)
BYPASS CAPACITORS
50 OHMS
GND
DNI
49.9100
R10
R47
R48
C40
C6
C39
R46
4
3
2
1
P1
R45
C37
C35
C5
C41
C36
C34
R44
R43
C31
J2
J3
C9
C10
R5
R4
R9
R3
C33
C32
R13
1
TP1
J4
J5
C15
21
C16
J6
J7
C17
C18
J8
J9
R15
R17
R16
R14
PAD
9
8
7
6
5
4
3
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
C11
C12
R8
R1
R6
R2
21
C2
21
C1J1
J0
C03
C04
R11
R08
5
4 3
1
T2
R12
R09
C3
C4
J11
J10
J14
R07
J15
VEE
DNI
GND
.1UF
MABA-007159-000000
OUT4B
OUT3B
200
VEE
VCC
200
VEE VEE
.1UF
0
GND
OUT4B
OUT2
GND
0
0
.1UF
.1UF
.1UF
0
Z5.531.3425.0
POWER
0
.1UF
.1UF
GND
10UF
VEE
VREF
.1UF
VT
.1UF
0
0
.1UF
200
200
200
200
GND
10UF
10UF
VREF
VT
.1UF
200
200
CP-24-2
VEE
200
200
.1UF
.1UF
OUT5B
OUT5
GND
0
VEE
GND
VEE
VCC
OUT1B
VEE
VEE
VCC
GND
GND
GND
GND
GND
GND
OUT2B
OUT2
VEE
VEE
VEE
VCC
VEEVEE
OUT4
VEE
OUT5
OUT5B
OUT0B
OUT0
GND
VREF
CLK
VEE
VT
CLKB
GND
GND
.1UF
.1UF
.1UF
OUT3
OUT3B
.1UF
VCC
VEE
OUT3
.1UF
CLK
.1UF
VEE
OUT4
.1UF
200
.1UF
GND
OUT0B
VEE
VCC
GND
VEE
0
VT
OUT1
OUT1
.1UF
GND
OUT1B
OUT2B
GND
.1UF
200
VEE
VEE
CLKB
ADCLK946
GND
49.9
0
DNI
OUT0
SECPRI
08668-004
Figure 4. ADCLK946 Evaluation Board Schematic
UG-069 Evaluation Board User Guide
Rev. 0 | Page 6 of 8
08668-005
Figure 5. Top Trace Layer
08668-006
Figure 6. Ground Plane Layer
P1-P3P4-P6P7-P8

ADCLK946/PCBZ

Mfr. #:
Buy ADCLK946/PCBZ
Manufacturer:
Analog Devices Inc.
Description:
Clock & Timer Development Tools EVAL BRD ADCLK946
Lifecycle:
New from this manufacturer.
Delivery:
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