MAX6401BS29+T

MAX6400–MAX6405
µP Supervisory Circuits in 4-Bump (2 2)
Chip-Scale Package
4 _______________________________________________________________________________________
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
0.2
0
0.6
0.4
1.2
1.0
0.8
1.4
-40 0-20 20 40 60 80
SUPPLY CURRENT vs. TEMPERATURE
MAX6400-05 toc01
TEMPERATURE (
°
C)
SUPPLY CURRENT (µA)
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 1.2V
0
50
150
100
200
250
-40 0-20 20 40 60 80
POWER-DOWN RESET DELAY
vs. TEMPERATURE
MAX6400-05 toc02
TEMPERATURE (
°
C)
RESET DELAY (µs)
V
OD
= 10mV
V
OD
= 20mV
V
OD
= 100mV
V
OD
= 200mV
V
OD
= OVERDRIVE VOLTAGE
130
150
140
170
160
200
190
180
210
-40 0-20 20 40 60 80
POWER-UP RESET TIMEOUT
vs. TEMPERATURE
MAX6400-05 toc03
TEMPERATURE (
°
C)
POWER-UP RESET TIMEOUT (ms)
0
1 100010010
MAXIMUM TRANSIENT DURATION
vs. THRESHOLD OVERDRIVE
500
200
100
400
300
MAX6400-05 toc04
THRESHOLD OVERDRIVE V
TH
- V
CC
(mV)
MAXIMUM TRANSIENT DURATION (µs)
RESET/RESET IS
ASSERTED
ABOVE LINE
Detailed Description
Reset Output
A microprocessors (µPs) reset input starts the µP in a
known state. These µP supervisory circuits assert reset
to prevent code execution errors during power-up,
power-down, or brownout conditions.
RESET is guaranteed to be a logic low for V
CC
down to
1V. Once V
CC
exceeds the reset threshold, an internal
timer keeps RESET low for the reset timeout period;
after this interval, RESET goes high.
If a brownout condition occurs (V
CC
dips below the
reset threshold), RESET goes low. Any time V
CC
goes
below the reset threshold, the internal timer resets to
zero, and RESET goes low. The internal timer starts
after V
CC
returns above the reset threshold, and RESET
remains low for the reset timeout period.
The manual reset input (MR) can also initiate a reset,
see the Manual Reset Input section. The MAX6401/
MAX6404 have active-high RESET outputs that are the
inverse of the MAX6400/MAX6402/MAX6403/MAX6405
outputs (Figure 1).
Manual Reset Input
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuit to initiate a reset. A logic low on MR asserts
reset. Reset remains asserted while MR is low, and for
the reset active timeout period (t
RP
) after MR returns
high. This input has an internal 50k pullup resistor, so
it can be left open if it is not used. MR can be driven
with TTL or CMOS logic levels, or with open-drain/col-
lector outputs. Connect a normally open momentary
switch from MR to GND to create a manual reset func-
tion; external debouncing circuitry is not required. If MR
is driven from long cables or if the device is used in a
noisy environment, connect a 0.1µF capacitor from MR
to ground to provide additional noise immunity (see
Figure 1).
Applications Information
Interfacing to µP with Bidirectional
Reset Pins
Since the RESET output on the MAX6402/MAX6405 is
open-drain, these devices interface easily with (µPs)
that have bidirectional reset pins. Connecting the µP
supervisors RESET output directly to the microcon-
trollers (µCs) RESET pin with a single pullup resistor
allows either device to assert reset (Figure 2).
Negative-Going VCC Transients
These devices are relatively immune to short-duration,
negative-going V
CC
transients (glitches).
The Typical Operating Characteristics show the
Maximum Transient Duration vs. Reset Threshold
Overdrive graph, for which reset pulses are not gener-
MAX6400–MAX6405
µP Supervisory Circuits in 4-Bump (2 2)
Chip-Scale Package
_______________________________________________________________________________________ 5
PIN
MAX6400/MAX6402
MAX6403/MAX6405
MAX6401/MAX6404
NAME FUNCTION
A1 A1 GND Ground
B1 RESET
Active-Low Reset Output, (Open-Drain or Push-Pull). RESET
is asserted low when the V
CC
input is below the selected
reset threshold. RESET remains low for the reset timeout
period after V
CC
exceeds the device reset threshold. Open-
drain outputs require an external pullup resistor.
B1 RESET
Active-High Reset Output. RESET remains high while V
CC
is
below the reset threshold and for at least 100ms after V
CC
rises above the reset threshold.
B2 B2 MR
Active-Low Manual Reset. Internal 50k pullup to V
CC
. Pull
low to assert a reset. Reset remains asserted as long as MR
is low and for the reset timeout period after MR goes high.
Leave unconnected or connect to V
CC
if unused.
A2 A2 V
CC
Supply Voltage and Input for the Reset Threshold Monitor
Pin Description
MAX6400–MAX6405
ated. The graph shows the maximum pulse width that a
negative going V
CC
transient may typically have when
issuing a reset signal. As the amplitude of the transient
increases, the maximum allowable pulse width
decreases.
Chip Information
TRANSISTOR COUNT: 512
PROCESS: BiCMOS
µP Supervisory Circuits in 4-Bump (2 2)
Chip-Scale Package
6 _______________________________________________________________________________________
RESET
INPUT
V
CC
µP
MAX6402/
MAX6405
V
CC
RESET
MOTOROLA
68HCXX
GND
GND
V
CC
MR
Figure 2. Interfacing to µPs with Bidirectional Reset Pins
V
CC
RESET
MR
V
TH
t
RD
t
RP
t
MR
t
RP
Figure 1. Reset Timing Diagram

MAX6401BS29+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits uPower Supervisor
Lifecycle:
New from this manufacturer.
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