MAX9378EUA+T Datasheet MAX9378EUA+, MAX9378EUA+T | P4-P6

MAX9377/MAX9378

Anything-to-LVPECL/LVDS Translators

with Pin-Selectable Divide-by-Four

4 _______________________________________________________________________________________

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Reset-to-Differential Output Low

Delay

Figure 4 0.8 1.0 ns

Reset-to-Input Clock Setup Time t

SET

Figure 4 0.5 ns

Clock-to-Divider Output

Propagation Delay

PCO

Figure 4 (Note 5) 0.6 1.0 ns

SEL to Switched Output Delay t

SEL

Figure 5 0.3 0.6 ns

MAX9377

Switching Frequency f

MAX

- V

≥ 250mV 2.0 2.5 GHz

Propagation Delay Low to High t

PLH

Figure 3, SEL = 0 250 421 600 ps

Propagation Delay High to Low t

PHL

Figure 3, SEL = 0 250 421 600 ps

Pulse Skew |t

PLH

-t

PHL

SKEW

(Note 6) 6 30 ps

Output Low-to-High Transition

Time (20% to 80%)

Figure 3 116 220 ps

Output High-to-Low Transition

Time (20% to 80%)

Figure 3 116 220 ps

Added Random Jitter t

= 1.34GHz (Note 7), SEL = 0 0.7 2 ps

(

RMS

)

MAX9378

Switching Frequency f

MAX

≥ 250mV 2.0 2.5 GHz

Propagation Delay Low to High t

PLH

Figure 3, SEL = 0 250 363 600 ps

Propagation Delay High to Low t

PHL

Figure 3, SEL = 0 250 367 600 ps

Pulse Skew |t

PLH

- t

PHL

SKEW

Figure 3 (Note 6) 3 30 ps

Output Low-to-High Transition

Time (20% to 80%)

Figure 2 93 220 ps

Output High-to-Low Transition

Time (20% to 80%)

Figure 2 93 220 ps

Added Random Jitter t

= 1.34GHz (Note 7), SEL = 0 0.8 2 ps

(

RMS

)

Note 1: Measurements are made with the device in thermal equilibrium. All voltages are referenced to ground except V

THD

, V

, and ∆V

Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.

Note 3: DC parameters production tested at T

= +25°C and guaranteed by design and characterization over the full operating

temperature range.

Note 4: Guaranteed by design and characterization, not production tested. Limits are set at ±6 sigma.

Note 5: t

PCO

is the delay associated with the frequency-divider function. The total delay when divide-by-four is selected is t

PCO

PLH

Note 6: t

SKEW

is the magnitude difference of differential propagation delays for the same output under same conditions; t

SKEW

PHL

- t

PLH

Note 7: Device jitter added to the input signal.

AC ELECTRICAL CHARACTERISTICS

= +3.0V to +3.6V, differential input voltage |V

| = 0.1V to 1.2V, input frequency ≤ 1.34GHz, differential input transition time =

125ps (20% to 80%), input voltage (V

, V

) = 0 to V

, input common-mode voltage V

= 0.05V to (V

- 0.05V), LVPECL outputs

terminated with 50Ω ±1% to (V

- 2.0V) MAX9377, LVDS outputs terminated with R

= 100Ω ±1% (MAX9378), T

= -40°C to +85°C.

Typical values are at V

= +3.3V, |V

| = 0.2V, input common-mode voltage V

= 1.2V, T

= +25°C, unless otherwise noted.)

(Note 4)

MAX9377/MAX9378

Anything-to-LVPECL/LVDS Translators

with Pin-Selectable Divide-by-Four

_______________________________________________________________________________________ 5

Typical Operating Characteristics

= +3.3V, differential input voltage |V

| = 0.2V, V

= 1.2V, input frequency = 500MHz, outputs terminated with 50Ω ±1% to

- 2.0V (MAX9377), outputs terminated with 100Ω ±1% (MAX9378), T

= +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. FREQUENCY

MAX9377/78 toc01

FREQUENCY (MHz)

SUPPLY CURRENT (mA)

0 1000500 1500 2000

MAX9378

MAX9377 NO LOAD

MAX9377

300

500

400

700

600

800

900

0 1000500 1500 2000

OUTPUT AMPLITUDE vs. FREQUENCY

MAX9377/78 toc02

FREQUENCY (MHz)

OUTPUT AMPLITUDE (mV)

MAX9378

MAX9377

300

360

340

320

380

400

420

440

460

480

500

-40 10-15 35 60 85

PROPAGATION DELAY

vs. TEMPERATURE

MAX9377/78 toc03

TEMPERATURE (

PROPAGATION DELAY (ps)

PLH

(MAX9377)

PHL

(MAX9377)

PLH

(MAX9378)

PHL

(MAX9378)

110

100

130

120

140

-40 10-15 35 60 85

OUTPUT RISE/FALL TIME

vs. TEMPERATURE

MAX9377/78 toc04

TEMPERATURE (

OUTPUT RISE/FALL TIME (ps)

(MAX9377)

(MAX9378)

MAX9377/MAX9378

Detailed Description

The MAX9377/MAX9378 are fully differential, high-

speed, low-jitter anything-to-LVPECL and anything-to-

LVDS translators, respectively, with a selectable

divide-by-four function. Low propagation delay and

high speed make them ideal for various high-speed

network routing and backplane applications at speeds

up to 2GHz in nondivide mode.

The MAX9377/MAX9378 accept any differential input

signals within the supply rails and with a minimum

amplitude of 100mV. Inputs are fully compatible with

the LVDS, LVPECL, HSTL, and CML differential signal-

ing standards. The MAX9377 outputs are LVPECL and

have sufficient current to drive 50Ω transmission lines.

The MAX9378 outputs are LVDS and conform to the

ANSI EIA/TIA-644 LVDS standard.

Inputs

Inputs have a wide common-mode range of 0.05V to

- 0.05V), which accommodates any differential sig-

nals within the supply rails, and requires a minimum of

100mV to switch the outputs. This allows the

MAX9377/MAX9378 inputs to support virtually any differ-

ential signaling standard.

RST and SEL Inputs

The frequency-divide functions are controlled by two

LVCMOS/LVTTL inputs, RST and SEL. SEL selects

either the divide-by-four function or a no-division func-

tion as shown in Table 1. RST, an asynchronous active-

high input, resets the divide-by-four within the device

and places the circuits into a known state. Setting RST

high when powering up the device with SEL high pre-

vents the unknown states with the divider from being

propagated to the outputs. If the device is powered up

with SEL high but without asserting RST, the outputs

are only guaranteed to be 1/4th the input frequency

after 2.5 cycles have been applied to the input.

LVPECL Outputs (MAX9377)

The MAX9377 LVPECL outputs are emitter followers

that require external resistive paths to a voltage source

= V

- 2.0V typ) more negative than worst-case

for proper static and dynamic operation. When

properly terminated, the outputs generate steady-state

voltage levels, V

or V

with fast transition edges

between state levels. Output current always flows into

the termination during proper operation.

LVDS Outputs (MAX9378)

The MAX9378 LVDS outputs require a resistive load to

terminate the signal and complete the transmission

loop. Because the device switches current and not volt-

age, the actual output voltage swing is determined by

the value of the termination resistor. With a 3.5mA typi-

cal output current, the MAX9378 produces an output

voltage of 350mV when driving a 100Ω load.

Anything-to-LVPECL/LVDS Translators

with Pin-Selectable Divide-by-Four

6 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 SEL

Frequency Divider Select Input. High = divide by four, low = no division. Internal 75kΩ pulldown to

GND.

2 IN Differential LVDS/Any Noninverting Input

3 IN Differential LVDS/Any Inverting Input

4 GND Ground

5 RST Frequency Divider Reset Input. Active high, asynchronous, reset. Internal 75kΩ pulldown to GND.

MAX9377 Differential LVPECL Inverting Output. Terminate with 50Ω ±1% to V

- 2V.

6 OUT

MAX9378 Inverting LVDS Output. Terminate to OUT with 100Ω ±1%.

MAX9377 Differential LVPECL Noninverting Output. Terminate with 50Ω ±1% to V

- 2V.

7 OUT

MAX9378 Noninverting LVDS Output. Terminate to OUT with 100Ω ±1%.

Positive Supply. Bypass from V

to GND with 0.1µF and 0.01µF ceramic capacitors. Place the

capacitors as close to the device as possible with the smaller value capacitor closest to the device

RST SEL OUTPUT

X L or open No frequency division.

H H Outputs are placed in differential low.

L H Divide-by-four function.

Table 1. SEL AND RST Truth Table

P1-P3 P4-P6 P7-P9

MAX9378EUA+T

Mfr. #:

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Manufacturer:

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Description:

Translation - Voltage Levels X-LVPECL/LVDS Translator

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MAX9378EUA+T

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