ADP3339AKCZ-1.8-RL

Data Sheet ADP3339
Rev. C | Page 9 of 12
THEORY OF OPERATION
The ADP3339 anyCAP LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider, consisting of R1 and R2, which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that equilibrium produces a
large, temperature-proportional input offset voltage that is repeata-
ble and very well controlled. The temperature-proportional
offset voltage is combined with the complementary diode volt-
age to form a virtual band gap voltage that is implicit in the
network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibil-
ity on the trade-off of noise sources that leads to a low noise design.
The R1/R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1/R2 resistor
divider is loaded by Diode D1 and a second divider consisting
of R3 and R4, the values can be chosen to produce a temperature-
stable output. This unique arrangement specifically corrects for
the loading of the divider, thus avoiding the error resulting from
base current loading in conventional circuits.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resis-
tance. Moreover, the ESR value required to keep conventional
LDOs stable changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.
With the ADP3339 anyCAP LDO, this is no longer true. The
ADP3339 can be used with virtually any good quality capacitor,
with no constraint on the minimum ESR. This innovative
design allows the circuit to be stable with just a small 1 μF
capacitor on the output. Additional advantages of the pole-
splitting scheme include superior line noise rejection and very
high regulator gain, which lead to excellent line and load
regulation. An impressive ±1.5% accuracy is guaranteed over
line, load, and temperature.
Additional features of the circuit include current limit and
thermal shutdown.
V
IN
OUT
ADP3339
C1
1
μ
F
C2
1
μ
F
V
OUT
GNDIN
02191-0-021
Figure 20. Typical Application Circuit
PTAT
V
OS
g
m
NONINVERTING
WIDEBAND
DRIVER
INPUT
Q1
ADP3339
COMPENSATION
CAPACITOR
ATTENUATION
(V
BANDGAP
/V
OUT
)
R1
D1
R2
R3
R4
OUTPUT
PTAT
CURRENT
(a)
GND
C
LOAD
R
LOAD
02191-0-020
Figure 21. Functional Block Diagram
ADP3339 Data Sheet
Rev. C | Page 10 of 12
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The stability and transient response of the LDO is a function of
the output capacitor. The ADP3339 is stable with a wide range
of capacitor values, types, and ESR (anyCAP). A capacitor as low as
1 μF is all that is needed for stability. A higher capacitance may
be necessary if high output current surges are anticipated, or if
the output capacitor cannot be located near the output and
ground pins. The ADP3339 is stable with extremely low ESR
capacitors (ESR ≈ 0) such as multilayer ceramic capacitors
(MLCC) or OSCON. Note that the effective capacitance of
some capacitor types falls below the minimum over tempera-
ture or with dc voltage.
Input Capacitor
An input bypass capacitor is not strictly required but is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1 μF capacitor from the input
to ground reduces the circuits sensitivity to PC board layout
and input transients. If a larger output capacitor is necessary, a
larger value input capacitor is also recommended.
OUTPUT CURRENT LIMIT
The ADP3339 is short-circuit protected by limiting the pass
transistors base drive current. The maximum output current is
limited to about 3 A. See Figure 16.
THERMAL OVERLOAD PROTECTION
The ADP3339 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. Thermal
protection limits the die temperature to a maximum of 160°C.
Under extreme conditions (that is, high ambient temperature
and power dissipation) where the die temperature starts to rise
above 160°C, the output current is reduced until the die tempera-
ture has dropped to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the devices power dissipation should be externally
limited so that the junction temperature does not exceed 150°C.
CALCULATING POWER DISSIPATION
Device power dissipation is calculated as follows:
P
D
= (V
IN
V
OUT
) × I
LOAD
+ (V
IN
× I
GND
)
where I
LOAD
and I
GND
are the load current and ground current,
and V
IN
and V
OUT
are the input and output voltages, respectively.
Assuming worst-case operating conditions are I
LOAD
= 1.5 A,
I
GND
= 14 mA, V
IN
= 3.3 V, and V
OUT
= 2.5 V, the device power
dissipation is
P
D
= (3.3 V – 2.5 V) × 1500 mA + (3.3 V × 14 mA) = 1246 mW
Therefore, for a junction temperature of 125°C and a maximum
ambient temperature of 85°C, the required thermal resistance
from junction to ambient is
C/W1.32
W246.1
C85C125
°=
°
°
=
JA
θ
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
The thermal resistance, θ
JA
, of SOT-223 is determined by the
sum of the junction-to-case and the case-to-ambient thermal
resistances. The junction-to-case thermal resistance, θ
JC
, is
determined by the package design and specified at 26.8°C/W.
However, the case-to-ambient thermal resistance is determined
by the printed circuit board design.
As shown in Figure 22, the amount of copper onto which the
ADP3339 is mounted affects thermal performance. When
mounted onto the minimal pads of 2 oz. copper (see Figure 22a),
θ
JA
is 126.6°C/W. Adding a small copper pad under the
ADP3339 (see Figure 22b) reduces the θ
JA
to 102.9°C/W.
Increasing the copper pad to 1 square inch (see Figure 22c)
reduces the θ
JA
even further, to 52.8°C/W.
02191-0-022
cab
Figure 22. PCB Layouts
Use the following general guidelines when designing printed
circuit boards:
1. Keep the output capacitor as close to the output and
ground pins as possible.
2. Keep the input capacitor as close to the input and ground
pins as possible.
3. PC board traces with larger cross sectional areas remove
more heat from the ADP3339. For optimum heat transfer,
use thick copper and use wide traces.
4. The thermal resistance can be decreased by adding a
copper pad under the ADP3339, as shown in Figure 22b.
5. If possible, use the adjacent area to add more copper
around the ADP3339. Connecting the copper area to the
output of the ADP3339, as shown in Figure 22c, is best, but
thermal performance is improved even if it is connected to
other pins.
6. Use additional copper layers or planes to reduce the
thermal resistance. Again, connecting the other layers to
the output of the ADP3339 is best, but is not necessary.
When connecting the output pad to other layers, use
multiple vias.
Data Sheet ADP3339
Rev. C | Page 11 of 12
OUTLINE DIMENSIONS
*
COMPLIANT TO JEDEC STANDARDS TO-261-AA
WITH THE EXCEPTION TO LEAD WIDTH.
103107-A
4.60 BSC
16°
10°
16°
10°
10° MAX
0.75 MIN
0.25
321
2.30
BSC
*
0.85
0.70
0.65
1.70
1.50
1.05
0.85
0.10
0.02
1.30
1.10
0.35
0.26
0.24
*
3.15
3.00
2.95
3.70
3.50
3.30
7.30
7.00
6.70
6.70
6.50
6.30
SEATING
PLANE
GAUGE
PLANE
Figure 23. 3-Lead Small Outline Transistor Package [SOT-223]
(KC-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Output Voltage (V) Package Description Package Option
2
Branding
ADP3339AKC-1.5-RL −40°C to +85°C 1.5 3-Lead SOT-223 KC-3
ADP3339AKCZ-1.5-RL −40°C to +85°C 1.5 3-Lead SOT-223 KC-3 L1C
ADP3339AKCZ-1.5-R7 −40°C to +85°C 1.5 3-Lead SOT-223 KC-3 L1C
ADP3339AKCZ-1.8-RL −40°C to +85°C 1.8 3-Lead SOT-223 KC-3 L19
ADP3339AKCZ-1.8-R7 −40°C to +85°C 1.8 3-Lead SOT-223 KC-3 L19
ADP3339AKCZ-2.5-RL −40°C to +85°C 2.5 3-Lead SOT-223 KC-3 L1D
ADP3339AKCZ-2.5-R7 −40°C to +85°C 2.5 3-Lead SOT-223 KC-3 L1D
ADP3339AKC-2.85-RL −40°C to +85°C 2.85 3-Lead SOT-223 KC-3
ADP3339AKCZ-3-R7 −40°C to +85°C 3.0 3-Lead SOT-223 KC-3 L3F
ADP3339AKC-3.3-RL −40°C to +85°C 3.3 3-Lead SOT-223 KC-3 L1A
ADP3339AKCZ-3.3-RL −40°C to +85°C 3.3 3-Lead SOT-223 KC-3 L1A
ADP3339AKCZ-3.3-R7 −40°C to +85°C 3.3 3-Lead SOT-223 KC-3 L1A
ADP3339AKCZ-5-R7 −40°C to +85°C 5 3-Lead SOT-223 KC-3 L3G
1
Z = RoHS Compliant Part.
2
This package option is halide free.

ADP3339AKCZ-1.8-RL

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Linear Voltage Regulators High-Acc 1.5A Ultralow IQ
Lifecycle:
New from this manufacturer.
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