1. General description
The PCA9515A is a CMOS integrated circuit intended for application in I
2
C-bus and
SMBus systems.
While retaining all the operating modes and features of the I
2
C-bus system, it permits
extension of the I
2
C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus
enabling two buses of 400 pF.
The I
2
C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9515A enables the system designer to isolate two halves of a bus, thus
more devices or longer length can be accommodated. It can also be used to run two
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the
100 kHz bus is isolated when 400 kHz operation of the other is required.
Two or more PCA9515As cannot be put in series. The PCA9515A design does not
allow this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage
levels are used to avoid lock-up conditions between the input and the output. A ‘regular
LOW’ applied at the input of a PCA9515A will be propagated as a ‘buffered LOW’ with a
slightly higher value. When this ‘buffered LOW’ is applied to another PCA9515A,
PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A
will not recognize it as a ‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again.
The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in
series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with
themselves since they use shifting instead of static offsets to avoid lock-up conditions.
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring.
2. Features and benefits
2-channel, bidirectional buffer
I
2
C-bus and SMBus compatible
Active HIGH repeater enable input
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard-mode and Fast-mode I
2
C-bus devices and multiple masters
Powered-off high-impedance I
2
C-bus pins
Operating supply voltage range of 2.3 V to 3.6 V
5.5 V tolerant I
2
C-bus and enable pins
PCA9515A
I
2
C-bus repeater
Rev. 5 — 23 March 2012 Product data sheet
PCA9515A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 23 March 2012 2 of 20
NXP Semiconductors
PCA9515A
I
2
C-bus repeater
0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be
less than 400 kHz because of the delays added by the repeater)
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO8, TSSOP8 (MSOP8), HWSON8
3. Ordering information
[1] Also known as MSOP8.
4. Functional diagram
Table 1. Ordering information
T
amb
=
40
C to +85
C.
Type number Topside
mark
Package
Name Description Version
PCA9515AD PA9515A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9515ADP 9515A TSSOP8
[1]
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
PCA9515ATP 15A HWSON8 plastic thermal enhanced very very thin small outline package;
no leads; 8 terminals; body 2 3 0.8 mm
SOT1069-2
Fig 1. Functional diagram of PCA9515A
002aad738
PCA9515A
SDA0
SCL0
EN
SDA1
SCL1
V
CC
GND
pull-up
resistor
PCA9515A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 23 March 2012 3 of 20
NXP Semiconductors
PCA9515A
I
2
C-bus repeater
5. Pinning information
5.1 Pinning
5.2 Pin description
[1] HWSON8 package die supply ground is connected to both GND pin and exposed center pad. GND pin
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper head conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8
(MSOP8)
Fig 4. Pin configuration for HWSON8
n.c. V
CC
SCL0 SCL1
SDA0
SDA1
GND EN
002aad736
1
2
3
4
6
5
8
7
PCA9515AD
PCA9515ADP
n.c. V
CC
SCL0 SCL1
SDA0 SDA1
GND EN
002aad737
1
2
3
4
6
5
8
7
SDA0
GND
EN
SDA1
SCL0
n.c.
V
CC
SCL1
002aag783
terminal 1
index area
1
PCA9515ATP
Transparent top view
2
3
4
8
7
6
5
Table 2. Pin description
Symbol Pin Description
SO8, TSSOP8 HWSON8
n.c. 1 7 not connected
SCL0 2 8 serial clock bus 0; open-drain 5 V tolerant I/O
SDA0 3 1 serial data bus 0; open-drain 5 V tolerant I/O
GND 4 2
[1]
supply ground (0 V)
EN 5 3 active HIGH repeater enable input
(internal pull-up with 100 k)
SDA1 6 4 serial data bus 1; open-drain 5 V tolerant I/O
SCL1 7 5 serial clock bus 1; open-drain 5 V tolerant I/O
V
CC
8 6 supply voltage

PCA9515AD,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Signal Buffers, Repeaters I2C BUS REPEATER
Lifecycle:
New from this manufacturer.
Delivery:
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