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PCA9515ADP/DG,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
PCA9515A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 23 March 2012 4 of 20
NXP Semiconductors
PCA9515A
I
2
C-bus repeater
6. Functional description
Refer to Figure 1 “Functional diagram of PCA9515A”.
The PCA9515A integrated circuit contains two identical buffer circuits which enable
I
2
C-bus and similar bus systems to be extended without degradation of system
performance.
The PCA9515A contains two bidirectional, open-drain buffers specifically designed to
support the standard LOW-level contention arbitration of the I
2
C-bus. Except during
arbitration or clock stretching, the PCA9515A acts like a pair of non-inverting, open-drain
buffers, one for SDA and one for SCL.
6.1 Enable
The EN pin is active HIGH with an internal pull-up and allows the user to select when the
repeater is active. This can be used to isolate a badly behaved slave on power-up until
after the system power-up reset. It should never change state during an I
2
C-bus operation
because disabling during a bus operation will hang the bus and enabling part way through
a bus cycle could confuse the I
2
C-bus parts being enabled.
The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.
6.2 I
2
C-bus systems
As with the standard I
2
C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I
2
C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard-mode and
Fast-mode I
2
C-bus devices in addition to SMBus devices. Standard-mode I
2
C-bus
devices only specify 3 mA output drive; this limits the termination current to 3 mA in a
generic I
2
C-bus system where Standard-mode devices and multiple masters are possible.
Under certain conditions higher termination currents can be used.
Please see Application Note AN255, I
2
C/SMBus Repeaters, Hubs and Expanders for
additional information on sizing resistors and precautions when using more than one
PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction
with the P82B96.
PCA9515A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 23 March 2012 5 of 20
NXP Semiconductors
PCA9515A
I
2
C-bus repeater
7. Application design-in information
A typical application is shown in Figure 5. In this example, the system master is running
on a 3.3 V I
2
C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz
unless the slave bus is isolated and then the master bus can run at 400 kHz. Master
devices can be placed on either bus.
The PCA9515A is 5 V tolerant, so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9515A is pulled LOW by a device on the I
2
C-bus, a CMOS
hysteresis type input detects the falling edge and causes the internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9515A will typically be at V
OL
=0.5V.
In order to illustrate what would be seen in a typical application, refer to Figure 6
and
Figure 7
. If the bus master in Figure 5 were to write to the slave through the PCA9515A,
we would see the waveform shown in Figure 6
on bus 0. This looks like a normal I
2
C-bus
transmission until the falling edge of the eighth clock pulse. At that point, the master
releases the data line (SDA) while the slave pulls it LOW through the PCA9515A.
Because the V
OL
of the PCA9515A is typically round 0.5 V, a step in the SDA will be seen.
After the master has transmitted the ninth clock pulse, the slave releases the data line.
On the bus 1 side of the PCA9515A, the clock and data lines would have a positive offset
from ground equal to the V
OL
of the PCA9515A. After the eighth clock pulse the data line
will be pulled to the V
OL
of the slave device, which is very close to ground in this example.
It is important to note that any arbitration or clock stretching events on bus 1 require that
the V
OL
of the PCA9515A (see V
OL
V
ILc
in Section 9 “Static characteristics”) to be
recognized by the PCA9515A and then transmitted to bus 0.
Fig 5. Typical application
002aad739
V
CC
PCA9515A
SDA0 SDA1
SCL0 SCL1
EN
10 kΩ
10 kΩ
SDA
SCL
BUS
MASTER
400 kHz
SLAVE
100 kHz
SDA
SCL
bus 0 bus 1
5 V
3.3 V
10 kΩ
10 kΩ
PCA9515A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 23 March 2012 6 of 20
NXP Semiconductors
PCA9515A
I
2
C-bus repeater
8. Limiting values
Fig 6. Bus 0 waveform
9
th
clock pulse
V
OL
of master
V
OL
of PCA9515A
002aad740
SCL
SDA
Fig 7. Bus 1 waveform
9
th
clock pulse
V
OL
of slave
V
OL
of PCA9515A
002aad741
SCL
SDA
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to pin GND.
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
V
I2C-bus
I
2
C-bus voltage SCL or SDA 0.5 +7 V
I
I/O
input/output current DC; any pin - 50 mA
P
tot
total power dissipation - 100 mW
T
stg
storage temperature 55 +125 C
T
amb
ambient temperature operating in free air 40 +85 C
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PCA9515ADP/DG,118

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Buy PCA9515ADP/DG,118
Manufacturer:
NXP Semiconductors
Description:
IC REDRIVER I2C 1CH 8TSSOP
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