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ADRF5024BCCZN

P1-P3P4-P6P7-P9P10-P12P13-P13
Data Sheet ADRF5024
Rev. A | Page 7 of 13
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = 3.3 V, VSS = −3.3 V, V
CTRL
= 0 V or VDD, and T
CASE
= 25°C for a 50 Ω system, unless otherwise noted.
Insertion loss and return loss are measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins.
However, signal coupling between the probes limits the isolation performance of the ADRF5024. Isolation is measured on the evaluation
board. See the Applications Information section for details on the evaluation and probe matrix boards.
16011-007
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0
5
10
15
20
25
30
35
40
45
50
INSERTION LOSS (dB)
FREQUENCY (GHz)
Figure 7. Insertion Loss vs. Frequency with Impedance Match
–40
–35
–30
–25
–20
–15
–10
–5
0
0
5
10
15
20
25
30
35
40
45
50
RETURN LOSS (dB)
FREQUENC
Y (GHz)
RFC
RF1 ON
RF2 ON
16011-008
Figure 8. Return Loss vs. Frequency for RFC and RFx (On)
with Impedance Match
–80
–70
–60
–50
–40
–30
–20
–10
0
0
5
10
15
20 25
30
35
40 45
50
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RFx
RFx TO RFx
16011-009
Figure 9. Isolation vs. Frequency with Impedance Match
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0 5 10
15 20 25
30 35
40
45 50
INSERTION LOSS (dB)
FREQUENC
Y (GHz)
16011-010
Figure 10. Insertion Loss vs. Frequency Without Impedance Match
–40
–35
–30
–25
–20
–15
–10
–5
0
0 5 10 15 20 25 30 35 40 45 50
RETURN LOSS (dB)
FREQUENCY (GHz)
RFC
RF1 ON
RF2 ON
16011-011
Figure 11. Return Loss vs. Frequency for RFC and RFx (On)
Without Impedance Match
–80
–70
–60
–50
–40
–30
–20
–10
0
0
5
10
15
20
25
30
35
40
45
50
ISOLATION (dB)
FREQUENCY (GHz)
RFC TO RFx
RFx TO RFx
16011-012
Figure 12. Isolation vs. Frequency Without Impedance Match
ADRF5024 Data Sheet
Rev. A | Page 8 of 13
INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT
VDD = 3.3 V, VSS = −3.3 V, V
CTRL
= 0 V or VDD, and T
CASE
= 25°C for a 50 Ω system, unless otherwise noted. All of the large signal
performance parameters were measured on the evaluation board.
10
12
14
16
18
20
22
24
26
28
30
0
5
10
15
20
25
30
35
40
INPUT P1dB (dBm)
FREQUENCY
(GHz)
16011-013
Figure 13. Input P1dB vs. Frequency
20
25
30
35
40
45
50
55
60
0 5 10
15 20 25 30 35 40
INPUT IP3 (dBm)
FREQUENCY (GHz)
16011-014
Figure 14. Input IP3 vs. Frequency
10
12
14
16
18
20
22
24
26
28
30
10k 100k 1M 10M 100M 1G
INPUT P1dB (dBm)
FREQUENCY (Hz)
16011-015
Figure 15. Input P1dB vs. Frequency (Low Frequency Detail)
20
25
30
35
40
45
50
55
60
10k 100k 1M 10M
100M
1G
INPUT IP3 (dBm)
FREQUENCY
(Hz)
16011-016
Figure 16. Input IP3 vs. Frequency (Low Frequency Detail)
Data Sheet ADRF5024
Rev. A | Page 9 of 13
THEORY OF OPERATION
The ADRF5024 requires a positive supply voltage applied to the
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
filter high frequency noise.
All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V,
and no dc blocking is required at the RF ports when the RF line
potential is equal to 0 V.
The RF ports are internally matched to 50 Ω. Therefore,
external matching networks are not required. However,
impedance matching on transmission lines can be used to
improve insertion loss and return loss performance at high
frequencies.
The ADRF5024 integrates a driver to perform logic functions
internally and provides the user with the advantage of a
simplified CMOS/LVT TL-compatible control interface. This
driver features a single digital control input pin, CTRL. The
logic level applied to the CTRL pin determines which RF port is
in the insertion loss state and in the isolation state (see Table 5).
The unselected RF port of the ADRF5024 is reflective. The
isolation path provides high isolation between the unselected
port and the insertion loss path.
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up VDD.
3. Power up VSS.
4. Power up V
CTRL
, the digital control input. Powering
the digital control input before the VDD supply may
inadvertently forward bias and damage the internal ESD
protection structures.
5. Apply an RF input signal.
The ideal power-down sequence is the reverse order of the
power-up sequence.
Table 5. Control Voltage Truth Table
RF Path
Digital Control Input (V
CTRL
) RF1 to RFC RF2 to RFC
Low
Isolation (off)
Insertion loss (on)
High Insertion loss (on) Isolation (off)
P1-P3P4-P6P7-P9P10-P12P13-P13

ADRF5024BCCZN

Mfr. #:
Buy ADRF5024BCCZN
Manufacturer:
Analog Devices Inc.
Description:
RF Switch ICs 40GHz, Low Loss, Reflective, fast switch
Lifecycle:
New from this manufacturer.
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