reside on the same bus without address conflicts
(Table 9).
The address pin states are checked at POR and RESET
only, and the address data stays latched to reduce qui-
escent supply current due to the bias current needed
for high-Z state detection. The MAX6680/MAX6681 also
respond to the SMBus Alert Response slave address
(see the Alert Response Address section).
POR and UVLO
The MAX6680/MAX6681 have a volatile memory. To
prevent unreliable power-supply conditions from cor-
rupting the data in memory and causing erratic behav-
ior, a POR voltage detector monitors V
CC
and clears the
memory if V
CC
falls below 1.91V (typ, see Electrical
Characteristics). When power is first applied and V
CC
rises above 2.0V (typ), the logic blocks begin operating,
although reads and writes at V
CC
levels below 3.0V are
not recommended. A second V
CC
comparator, the ADC
UVLO comparator, prevents the ADC from converting
until there is sufficient headroom (V
CC
= 2.8V typ).
Power-Up Defaults
• Interrupt latch is cleared.
• Address select pin is sampled.
• ADC begins autoconverting at a 1Hz rate (legacy
resolution).
• Command register is set to 00h to facilitate quick
internal Receive Byte queries.
•T
HIGH
and T
LOW
registers are set to max and min
limits, respectively.
• Hysteresis is set to 6°C.
• Transistor type is set to a substrate or common-col-
lector PNP.
Temperature Offset
The MAX6680/MAX6681 are designed to provide ±1°C
accuracy for common microprocessors and discrete
transistors. To accommodate processes that differ sig-
nificantly in their ideality factor, the user can
increase/decrease the Remote Temperature Sensor
Data register with an offset by writing to the External
Offset High and Low Byte registers (11h and 12h,
respectively). The offset temperature data is represent-
ed as a 10 bits + sign with a 0.125LSB resolution.
MAX6680/MAX6681
±1°C Fail-Safe Remote/Local Temperature
Sensors with SMBus Interface
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